by John O. Borland, Editorial Advisor, Solid State Technology
This year’s VLSI Symposium held June 14-17 in Kyoto, Japan was not as interesting (or contentious) as the past two years, led by presentations from Intel and IBM. In 2007 the hot topic was which high-k/metal gate (HK+MG) approach will be used and whether it would be delayed until the 32nm node; in 2008 the two hot topics were bulk or SOI CMOS and planar or FinFET for 22nm node.
However, Intel’s participation was obviously missing from this year’s VLSI Symposium, and the few papers from IBM this year reported on their process results to extend planar CMOS to 16nm node. “CMOS scaling will continue to 11nm node and maybe even 8nm,” proclaimed TC Chen, VP of IBM Research, in the 2nd plenary invited talk (1-3, see below). The key to extending planar CMOS to the 16nm node and beyond, as reported by others (see papers below: 9A-1, 12B-1, 12B-3, 12B-4), is using a Ge channel for pMOS and a III-V channel such as InGaAs for nMOS for mobility enhancement. This also explains why IMEC has changed their focus from FinFET to Ge-channel for pMOS and III-V channel for nMOS — though it is unclear if FinFET or FD-SOI will be embedded at 16nm or beyond. For HK+MG 1st process, everyone seems to be using a La capping layer for nMOS and Al capping layer for pMOS (see papers below: 3A-3, 3A-4, 11A-1, and 11A-4). And to continue gate scaling to the 16nm node for EOT <0.6nm, several reported using higher-k and eliminating the interfacial oxide layer (see papers below: 3A-1 and 7-2). But no clear picture emerged from speakers and panelists in this year’s short course and a rump session about what will be the 22nm and 16nm node technology.
In the short course, “Outlook for 32/28/22nm Manufacturing,” F. Boeuf of ST Microelectronics showed that the system-on-chip (SoC) market is driven by mobile applications and by age group. In the US, the top three usages for 12-17 year-olds are gaming, e-mail, and instant messaging, and for 18-63 year-olds the top two are e-mail and search. But the #3 usage for those aged 18-44 and 45-63 is looking up product information and health information, respectively. This all requires a broad spectrum of functionalities such as fast logic, low power, analog-RT, and embedded memories. So the number of different transistors per chip has increased from only two at 0.25μm technology to more than 27 at the 32nm node. With the increasing number of transistor and possible co-integration of device structures such as planar CMOS with FinFET CMOS, he said, the choice in the future will be System in package (SiP) or SoC, suggesting that SoC is suitable to low-end and stable production (high volume) while SiP and 3D-IC are suitable for high-end, quick time-to-market early production.
Today we have immersion lithography with double patterning which is extendable to the 22nm node. At some point beyond that EUV lithography will be needed, but the source is the most critical issue, noted H. Tanaka of Selete. He said the alpha-tools delivered in 2006-2007 show good performance but the throughput is 5-10 wafers/hour. Beta-tools scheduled for 2010 should increase throughput to 20-100wph, with the production tools in 2012 with 55-180 wph — thus EUVL is moving toward production, he concluded.
Discussing “low-power CMOS devices and applications,” H. Shinohara of Renesas said the key requirement for LSTP transistor is low leak current for Ioff, IG and Isub. IG reduction by going to high-k and higher-k, low I Ioff with shorter LG with channel control (SCE) by metal gate, and high Vt and low Isub by BTBT reduction. He also pointed out that variability both random and systematic must be reduced.
W. Haensch of IBM said that 22nm will possibly be the last generation of doping controlled planar devices, so fully depleted devices by either SOI or FinFET will be necessary. (However, AIST later stated [6A-5] that even undoped channel shows Vt variation due to metal gate grain size variation.) And everyone is waiting for EUV lithography, he added.
W.R. Bottoms of Third Millennium Test Solutions emphasized that with the use of the 3rd dimension, packaging will be the key enabler for SiP (system in package) using TSV for stack die-to-die connection.
T.C. Chen, VP of IBM research gave the invited 2nd plenary talk on “Device technology innovation for exascale computing” (1-3). The two main sources of device variability (to which sessions 6 and 8 were devoted) are line-edge-roughness (LER) and dopant distribution (also called random dopant fluctuation RDF). He also stated that CMOS scaling will continue to 11nm node and maybe even 8nm. With scaling, device performance degrades — from the 90nm to 45nm node the industry used boosters like stress (DSL, SMT and eSiGe). He also pointed out that the 90nm node gate oxide was 1.1nm, near the atomic limit of a few atoms — and atoms cannot scale — so for the 45nm node to the 22nm node HK+MG will be used. At the 16nm node ultra-thin body SOI of FinFET “body controlled devices” will be required to extend CMOS to 11nm and maybe even 8nm with nanowire FET CMOS. Even though silicon technology is slowing down, system performance improves, 4× every 2 years as shown below due to innovations in system architecture changes.
Acceleration in system performance. (Source: VLSI Sym paper 1-3 & IBM)
SEMATECH discussed gate-first HK+MG stacks with a zero SiOx interface, achieving EOT=0.59nm for 16nm [3A-1]. The two options, they said, for continued gate oxide scaling for lower EOT are either go to higher-k or reduce the IL (interfacial oxide layer). They achieved what they call “zero interfacial layer” (ZIL) and an EOT of 0.59nm and gate leakage of 3A/cm2. On the other hand, they also achieved a higher-k of 35 but the leakage was worse 100A/cm2.
Reducing interfacial oxide layer to 0.0nm meets 16nm node EOT and gate leakage. (Source: VLSI Sym paper 3A-1 & Sematech)
IMEC presented a very nice summary of their work on an optimized ultra-low thermal budget process flow for advanced HK+MG (first) CMOS using laser annealing [3A-3]. As many others have shown, IMEC reported using La capping of the HK for nMOS and Al capping of HK for pMOS and then mixing it with the HK material.
A joint paper by Renesas and Panasonic [3A-4] explored the impact of area scaling on threshold voltage lowering in La-containing HK+MG NMOS FETs, fabricated on (100) and (110) Si.
The rump session discussing “Key technology options for 16nm CMOS and beyond” was disappointing, lacking the spirit of past years. R. Jammy of SEMATECH reviewed their message from their VLSI Symposium papers (50% of EOT lost due to IL so key is ZIL, HK+MG with dual capping layer and defect free USJ). O. Faynot of CEA-LETI’s message was to use FD/SOI, especially Soitec’s new ultrathin SOI that is very uniform. W. Haensch of IBM said power is the limit so go to low voltage, but that will limit performance, so also use 3D Si integration. K. Kita of the University of Tokyo said go to higher high-k or thinner IL, but it will be limited by mobility degradation. K. Uchida of Tokyo Institute of Technology said to go with FinFETs or nanowires and use Ge-channel for pMOS and InGaAs for nMOS. C. Wann of TSMC declined to show any technical data.
Vt variability
MIRAI-Selete [6A-1], presenting an analysis of extra Vt variability sources in NMOS using Takeuchi Plot, stated that retrograde profile has the smallest effect on Vt variation. The heavier the dopant the better the Vt control, so retrograde looks best.
Toshiba offered an interesting paper (6A-3, “Physical understanding of Vth and Idsat variations in (110) CMOS FETs,” about the Vt implant dopant profile shape to reduce variation either graded, flat, or retrograded. MIRAI-Selete had a similar message (6A-4, “A new methodology for evaluating Vt variability considering dopant depth profile”).
In its paper [6A-5, “Comprehensive Analysis of Variability Sources of FinFET Characteristics”] AIST made an interesting statement that even undoped channel shows Vt variation due to metal gate grain size variation.
In paper 7-2 IBM discussed an “extremely scaled gate-first HK+MG stack” with EOT=0.55nm, using “novel interfacial layer scavenging techniques” — specifically, an unspecified HK capping layer for nMOS.
IBM also discussed its work in high-performance 32nm SOI CMOS using HK+MG and ultralow-k backend with 11 Cu levels [7-3]. They reported using eSiGe for pMOS, SMT for nMOS, and dual stress liners for both n & p MOS. Using HK+MG first they achieved Tinv=1.2nm with the PD-SOI structure. The SOI performance was 20% better than IBM’s bulk 32nm process, and they claim this is 12% better than other published 32nm results. They said they control junction leakage to control floating body effects.
LETI and STMicroelectronics jointly presented a paper on “GeOI and SOI 3D monolithic cell integration for high-density applications” [9A-1], showing how they succeeded in stacking Ge pMOS devices over Si nMOS devices with SOI and GeOI wafer bonding.
As mentioned before, it seems everyone is using single metal dual cap HK+MG stacked structure with La cap for nMOS and Al cap for pMOS with TiN metal. SEMATECH added its name to the list with its paper [11A-1] on “A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications.”
Another interesting paper from Toshiba [11A-4] studying mobility-Tinv tradeoff in deeply scaled HK+MG devices as well as scaling design guidelines for the 22nm node compared the trade-off between Tinv scaling and mobility degradation on drive current for long and narrow devices. They also use La doped HfSiON for nMOS.
SEMATECH’s paper [12B-1] on “Mechanisms for low on-state current of Ge (SiGe) nMOS FETs” — labeled as a “comparative study on gate stack, resistance, and orientation-dependent effective masses” — showed that the reason for poor Ge-nMOS drive current is the poor n-type dopant activation as shown below. This is why rather than using Ge-channel material for nMOS the industry is looking at III-V channel material like InGaAs for nMOS.
Comparison of n & p MOSFET on Si, SiGe 25%, SiGe 40% and Ge channels on (a) drain current-gate voltage and (b) transconductance. (Source: VLSI Sym paper 12B-1 & Sematech)
Comparison between p-Ge and n-Ge for contact resistance and specific contact resistivity. (Source: VLSI Sym paper 12B-1 & Sematech)
A joint paper from the U. of Tokyo, AIST, and Sumitomo Chemical ([12B-3], “High mobility metal S/D III-V-on-insulator MOSFETs on a Si substrate using direct wafer bonding”) showed how they used wafer bonding to realize InGaAs on insulator for nMOS.
The Nat. Univ. Singapore presented on strained InGaSa n-MOSFETs with its paper [12B-4], “Performance boost with in-situ doped lattice-mismatched source/drain stressors and interface engineering.” The alternative to Ge-channel for nMOS is to use III-V such as InGaAs instead, as demonstrated by NUS below. They also increased the tensile channel strain by reducing the In content in the elevated S/D from 53% in the channel to 40% in the elevated S/D structure. — J.O.B.
Process flow ad key process steps for InGaAs MOSFET with elevated S/D stressors. (Source: VLSI Sym paper 12B-4 & NUS)
John Borland is founder of J.O.B. Technologies, and a member of SST‘s Editorial Advisory Board.