July 1, 2009 — To gain a better understanding of how new and existing wafer metrology technologies can be used, modified, or enhanced to measure and improve 3D interconnect processes, SEMATECH will host a workshop dedicated to 3D interconnect metrology on July 15 in conjunction with SEMICON West in San Francisco, CA.

To further explore innovative metrology capabilities, workshop participants will share real metrology results from 3D interconnect processing, discuss metrology challenges, and define possible solutions for measuring films and high-aspect ratio features that dominate 3D architectures.

“We must have the 3D tooling infrastructure available and address the equipment concerns that have to be resolved before volume manufacturing can take place,” said Andrew Rudack, SEMATECH’s 3D equipment process engineer and workshop chair. “Through SEMATECH’s 3D Interconnect program and workshops such as this, attendees can compare progress and develop an assessment on integration approaches, process architectures, and tool sets that will make 3D TSVs commercially viable.”

The speaker line-up includes:

Metrology Applications of Enabling Technologies for Wafer Thinning, John Moore, Daetec
Scanning Acoustics Microscopy for Metrology of 3D Interconnect Bonded Wafers, James McKeon, Sonix
Through-Silicon Via (TSV) Processes Demand Macroscopic to Microscopic Metrology, Liam Cunnane, Metryx
3D Interconnect Bonded Wafer Pair Metrology Using IR Microscopy, Richard Poplawski, Olympus-ITA
A Route Towards Non-Destructive Three-Dimensional CD Measurements of Through Silicon Via with X-ray Computed Tomography, Steve Wang, Xradia
Optical Metrology for TSV Process Control, Matthew Knowles, Zygo
Aspect Ratio Independent Non-Contact, High Throughput TSV Depth Metrology for 3D Interconnect Technology, David Marx, Tamar
The half-day workshop will conclude with a panel discussion entitled “3D Metrology