Crystalline Si solar cells and the microelectronics experience

by K. Baert, E. Van Kerschaver, J. Poortmans, IMEC


A thin c-Si solar cell roadmap is expected to be instrumental for facilitating open innovation collaboration models, based on sharing of intellectual property and resources — an established means in the IC industry for enhanced collaboration.

Today, the PV industry is no doubt the faster growing branch of the silicon semiconductor industry. In 2008, it reached a turnover of $37.1 billion, representing growth of 110% over the previous year [1]. Key to sustaining such growth will be the economic competitiveness of photovoltaic electricity with conventional power plants. 2008 has seen the first announcements of PV systems claiming to have reached grid parity [2]. In the long term, PV will make pervasive inroads if the key component of the system, the PV module, can be fabricated at a price level as low as 0.5 Euro/Wp [3]. This price is realistic if the industry can reduce its cost along its historical learning curve [4].

Currently, crystalline Si (c-Si) PV dominates the PV market. The mainstream manufacturing approach today is to process silicon solar cells from Si wafers about 180μm thick, next to assemble these cells into PV modules. The production costs of this process are continuously lowered by improved manufacturing practices, increase of areal throughput of equipment, upscaling of fabs, and vertical integration within the value chain. Yet, reaching a cost target of 0.5 Euro/Wp does not seem possible, so innovative solar cell concepts will have to be introduced to bridge the gap [5, 6]. This implies the use of new materials, and new production techniques. The impact on c-Si PV process technology could be as disruptive as the introduction of Cu interconnects, low-k, and high-k materials have been to the IC industry. We describe here a roadmap for thin c-Si with emphasis on the opportunities of using materials and process methods used for IC manufacturing and packaging.

A thin crystalline Si solar cell roadmap

With Si representing about 40 % of the cost/Wp at module level [5, 6], the amount of Si used per Wp has to be reduced drastically from the present 8-9g/Watt. The other dominant cost factor is the assembly process of cells into modules — a cost made up largely by the material bill, and therefore scaling substantially with area. Expressed in cost/Wp, the module assembly cost can most readily be reduced by assembling more efficient PV cells. We believe that efficiencies of thin cells should be increased beyond 20%, from today’s level in the range of 15%-16%.

For cells much thinner than today’s 180μm, the influence of the non-illuminated side of the cell becomes increasingly important (at this side carriers can easily recombine due to the high number of surface defects). Traditional passivation schemes of solar silicon are based on silicon-nitride but this does not have a potential for cell types above 20%. To reach high efficiency targets in such thin cells it is necessary to reduce the minority carrier recombination. A first step in that direction is the i-PERC [7] process: the use of alternative dielectric passivation schemes resulted in cell efficiencies being almost independent to cell thickness reductions from 180μm to 120μm.

Figure 1. Crystalline silicon solar cell roadmap.
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In the longer term, negative charge dielectrics (e.g., Al2O3 deposited by thermal ALD) are expected to be even more promising. Recombination velocities as low as 10cm/s have been demonstrated [8] and the layers are now being implemented in industrial-style solar cells [4]. So far, the throughput of ALD systems has been limited, but several high-throughput pathways are under investigation.

Another trend is that doping profiles should be controlled more precisely than is possible by diffusion (the prevailing approach in production today). One objective is to better engineer the emitter profile (in order to increase the UV response of the cell and its open-circuit voltage). The other objective is to use boron for the back surface field — in an approach known as PERL [9] (most of today’s cell use an aluminium back surface field which is conveniently obtained from an aluminium back electrode but less efficient).

Epitaxial growth [10] and ion implantation [11] offer the required degree of precision, but the tools developed for the IC industry have proven to be ill-conceived to reach the required throughput of PV manufacturing lines (>1000wph). New types of equipment such as plasma immersion ion implantation [5] or batch-type epitaxial reactors promise higher throughput — the challenge will be to maintain a sufficiently wide process window tuned to the specific profiles required by PV cells.

Most of today’s Si solar cells have a grid-like electrical contact at the illuminated side and a planar contact at the non-illuminated side of the cell. To increase efficiencies even further, it is necessary to eliminate the “shadowing” of the grid-like contact and make cells with two contacts at the non-illuminated side — so-called “interdigitated back-contact cells” (i-BC) — in some way similar to a planar IC process. Such i-BC solar cells are already in production [12], but at today’s substrate thicknesses, they require premium wafers (very high minority carrier lifetime is needed to ensure that photo-generated carriers do not recombine inside the silicon wafer before reaching the back contacts). While this makes i-BC cells rather expensive today, our view is that once thin wafers become widely used, back-contact cells may become mainstream.

For the sake of completeness, it should be mentioned that, in addition to the reduction of Si cost, other opportunities for reducing the manufacturing cost of solar cells lie in substitution of expensive materials. Silver pastes used for the electrodes of solar cells could be substituted by Cu plating processes (derived from the PCB industry), combined with highly effective barrier layers (from high-density Cu interconnect technology).

Module integration and reliability

The trends to thinner cells also impose specific requirements towards integration into modules. The conventional tabbing and stringing process used today is prone to create cracks in thinner cells due to the thermo-mechanical stress of this assembly process. For back-contact cells, module integration schemes based on ‘flip-wafer’ mounting of the cells with conductive adhesives or solder balls on a laminate substrate have been demonstrated, but are not widely used yet [13]. An attractive alternative is a superstrate interconnection technology where back-contact thin cells are embedded on module glass by planar processing — based on concepts that have successfully been demonstrated for ultrathin ICs [7]. This approach can lead to material and manufacturing cost savings as compared to a substrate-based integration.

The changes in cell and module concepts described above and the proposed new materials cannot, however, be implemented in production if reliable operation over lifetime is not ensured. The research agenda therefore should include reliability testing and failure mode analysis in order to provide aging models that can predict operational lifetimes up to 35 years.

Disruptive cell concepts

In the previous discussion, we considered evolutionary changes building upon today’s manufacturing processes for silicon PV. But disruptive cell concepts are also vigorously explored, for example, by some US start-ups, which often operate in a stealth mode [14]. We describe here some of the pathways under study at IMEC.

The lower limit of scaling cell thickness is ultimately dictated by physics: for silicon, it is has been calculated that the optimum efficiency is reached at a thickness of 40μm [15]. Such U-cells (ultrathin cells of 40μm) cannot be produced with regular production technology. First of all, there exists no cost effective technology to produce high-quality ultrathin wafers. Wire sawing may be limited to 100μm, with a kerf loss equal to that width. More promising techniques are based on releasing thin foils directly from an ingot. Prototype wafers have been fabricated by Silicon Genesis [16] and SLIM-Cut (stress-induced lift-off method) [17]. With the latter technique, we have fabricated thin foils down to 50μm representing a savings of a factor of 6 in Si consumption.

Another challenge will be to develop yielding manufacturing processes for solar cells made out of such thin Si wafers. This will require fundamentally new wafer handling concepts, since the wafer is not rigid anymore by itself and somehow needs to be supported during its complete processing cycle. In addition, these ultra-thin cells are also ultra-sensitive to induced strain — so they will require stress-free conditions during the entire processing. Concepts proposed for 3D-integration and embedding of thinned IC may have an advantage here.

An entirely different pathway to work with very thin silicon layers is based on epitaxial solar cells, in which a thin (<20μm) high-quality Si active layer is grown epitaxially on a low-cost Si carrier substrate (metallurgical grade or ribbon Si). A porous Si reflector in-between both strongly improves the optical confinement of light in the active part of the cell. After the epitaxial growth on the buried porous Si reflector, the processing of the cell is generically similar to a standard process. In the lab, efficiencies of 16.1% (small area) have recently been achieved thanks to the use of a chirp-like reflector, which offers a broader reflection spectrum than a Bragg reflector [10].

Figure 2. Cross-section (a) and views (b) of an epi-cell.

The availability of high throughput epi-systems is still a major challenge for industrialization, different prototypes are now being developed. The epi-cell approach is disruptive in terms of cell architecture but actually still rather compatible with existing fab infrastructure (essentially, epitaxial and porodization process tools would substitute the diffusion and doped glass etching equipment in standard fabs). For non-integrated solar cell manufacturers, the epi-cell approach has an additional bonus: it makes them independent from the suppliers of silicon wafer (and the associated up and downs of Si wafer cost). Finally, the use of “any-thickness” low-cost wafers could also be the enabler to move from today’s 156mm × 156mm standard wafer size to 210mm × 210mm — a transition that has been predicted long ago but never materialized in the PV industry so far, due to the difficulties of upscaling wafers of 180μm thickness.

Eventually, the most attractive process for crystalline Si solar cells may be those that significantly shortcut the manufacturing flow from quartz sand to PV module. In this respect, Si thin film cells in which poly-crystalline Si layers are deposited directly from TCS or SiH4 on large-area non-Si substrates (such as glass) offer a significantly shorter manufacturing cycle because they eliminate the costly and lengthy ingot and wafering process of silicon. Industrialization of poly-Si thin-film cells will still require fundamental breakthroughs in terms of efficiency — which today is limited to <10% by the quality of the crystalline silicon layer [18]. If efficiencies of 15% can be achieved, the technique would become very competitive with other thin film approaches.


In the past, introduction of process changes in the existing solar cell lines was a relatively slow process, certainly when compared with the rapid technology evolution within the microelectronics sector. The above-mentioned reliability issues mean that PV manufacturers are not easily engaging in adventurous innovation in cell, or especially, module technology. Another problem was that innovation in process equipment has been evolutionary rather than revolutionary. Due to the increasing size of the existing industrial PV players and the entrance of new players stemming from the microelectronic sector with their strong background in semiconductor processing and the rapid implementation of new processes, the introduction of new technologies is surely going to be accelerated. Thanks to the increased size of the industry, the development of PV-dedicated equipment becomes economically more viable. In 2008, already 20% of the members of SEMI were active in the PV sector or analyzing the market to position their products [19].

We have proposed a roadmap for thin c-Si solar cells incorporating IC-like technologies and methodologies. Such roadmaps have proven to be instrumental in the past for open innovation collaboration models, based on sharing of intellectual property and resources, which have become an established means in the IC industry for enhanced collaboration between manufacturers, equipment vendors, and material suppliers. The PV industry is in many respects quite different from the IC industry, but the potential R&D synergies may be equally instrumental to the PV industry.


Kris Baert received his PhD from the Katholieke Universiteit Leuven (K.U.Leuven) and is Si-PV program manager at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium; ph : +32-16-28 7893; Fax: +32-16-28 1097; e-mail [email protected].

Emmanuel Van Kerschaver received his PhD from the Katholieke Universiteit Leuven (K.U.Leuven) and is group leader PV at IMEC.

Jef Poortmans received his PhD from the Katholieke Universiteit Leuven (K.U.Leuven) and is Department Manager and PV program director at IMEC.


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This article was originally published by Photovoltaiacs World.


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