Die-scale stress management to advanced annealing optimization

by David M. Owen, Jeff Hebb, Ultratech Inc.


Transistor-scale engineering of stress is being widely adopted in the effort to achieve performance targets for advanced technology nodes. Currently, much attention is given to the incorporation of e-SiGe for PMOS or e-Si:C for NMOS devices to improve channel mobility. Whereas stress management on the scale of the gate length is accepted as part of advanced process development, stress management on larger scales is often overlooked. Part of the reason for this may be due to the limitations of traditional stress metrology, which is typically unable to characterize within-die and die-to-die stress variations on patterned wafers. The research described in this article addresses these issues.

The CGS-300 stress metrology system was utilized to understand the role of within-wafer and process-to-process stress variations in downstream process issues and device performance variations. Numerous front-end processes were investigated; however particular attention was paid to stresses induced by RTP and millisecond annealing processes. Two case studies are provided: a) the role of stress gradients in mis-alignment at lithography, and b) the correlation of die-to-die stress variations to device performance variations. The implications of these two findings in the context of advanced annealing are also discussed; control of thermal processes is critical for stress management due to the possibility of strain relaxation and slip at elevated temperatures.

Overview of CGS technique

The coherent gradient sensing (CGS) interferometer uniquely enables the generation of full-wafer stress maps comprised of >700,000 points (310μm/point). The attributes of the CGS technique make it well suited for measuring a wide range of patterned wafers [1,2]. A 310mm diameter probe beam captures data from the whole wafer simultaneously, so high point density does not result in throughput reduction. This is in contrast to many other stress measurement approaches that collect data on a point-by-point basis to generate low density maps. The CGS system measures surface slope that is acquired in two orthogonal directions, typically parallel and perpendicular to the notch. The full-wafer slope data is integrated numerically to obtain the wafer topography, and differentiated to obtain curvatures. The curvature change can be used to calculate the corresponding stress-induced by a process using the Stoney formula [3].

By tracking stress using CGS across multiple process steps, a comprehensive picture of the stress evolution in a process flow can be obtained. The stress non-uniformity and stress magnitudes of a single process or multiple processes may cause significant issues at lithography and also contribute to device performance variations, as described in the following case studies.

Stress, deformation and lithography

The idea that extremely warped wafers may be challenging to expose within specification during lithography is not new. However, detailed knowledge of the relationship between wafer deformation and stress and lithography misalignment [2,4], or focus errors [5], is required if these issues are to be reduced and managed before wafers get to lithography. Recent work has demonstrated [2,4] that misalignment is proportional to stress gradients. A case study using this approach for characterizing stress-induced misalignment due to rapid thermal processing (RTP) is provided below, however the relationships between stress, deformation and lithography performance cited above can be used to quantitatively evaluate any individual step or series of steps in a process flow.

A series of experiments were performed to investigate the role of the temperature during RTP on stress uniformity and subsequent contact-to-gate misalignment. The wafer set included two different substrate types on which the same device was fabricated. At the RTP step, one of each substrate type was annealed at five temperatures. The temperatures chosen were equally distributed around the baseline. The wafers were measured using the CGS-300 immediately before and after RTP, to characterize the stress-induced by RTP. Otherwise, the processing of the 10 wafers was nominally identical. The misalignment was measured at the four corners for 15 fields (60 locations per wafer). The CGS-300 stress data was evaluated for each of these 60 locations and the local gradient quantities were calculated [2,4]:

where Qx and Qy are the CGS misalignment potential in the x- and y-directions, respectively, and the stress components in Cartesian coordinates are σxx, σyy and σxy. Note that the high point density of the CGS system uniquely enables the accurate determination of these gradient quantities anywhere on the wafer.

Figure 1 shows a plot of the normalized misalignment versus the CGS value, |Q|. Each point in Fig. 1 corresponds to the average of the 60 points measured per wafer. The linear fit (dashed line in Fig. 1) indicates excellent correlation with r2=0.86. The data in Fig. 1 demonstrates that the optimization of the RTP step results in a 33% reduction in misalignment. Additionally, note that the y-intercept of the dashed line in Fig. 1 represents the misalignment expected if the RTP-induced stress was uniform (i.e., ~0.16 a.u.), implying that a further improvement of >3× in misalignment might be realized if RTP stress non-uniformity was minimized. It should also be recognized that the intercept represents the misalignment that can be attributed to other sources, identifying RTP stress uniformity as the most significant contributor to misalignment (70%-82% of total).

Figure 1. Variation of the wafer average of lithographic misalignment with magnitude of the stress gradients induced during rapid thermal processing showing excellent correlation with r = 0.93.

Generally, the approach of characterizing the source of lithography misalignment using stress non-uniformity can be extended across multiple steps in a process flow to identify critical processes for overlay improvement. Such an approach will undoubtedly be useful in meeting the stringent overlay requirements at 32nm and beyond.

Correlations of stress variations to device performance variations

As noted in the introduction, the management of stress on the scale of the gate length is an accepted part of engineering advanced devices. However, these intentionally engineered stresses are susceptible to relaxation and modification during subsequent processing. Furthermore, stress-induced defects (e.g., dislocations, micro-cracks, etc.) may compromise device performance. By tracking wafers from process-to-process on a die level using the CGS-300, the influence of stress variations on device performance variation can be characterized quantitatively and critical process steps can be identified.

In this case study, a 24-wafer lot of a 65nm DSP device was tracked throughout the front-end from wafer start through source drain anneal. CGS-300 stress measurements were made at 15 points throughout the ~120 process steps. The stress data collected at each step and device performance data measured at the end of the line were evaluated for 21 die locations. Additional details of the process and analysis approach can be found elsewhere [6]. Previously, the relationship between stress and leakage current was reported, revealing that stress variations accounted for 41% and 49% of the leakage current variations for PMOS and NMOS, respectively [6]. For this report, the correlation between stress and other parameters has been explored.

Figure 2. Variation of drain current with die-level stresses measured across multiple steps for a) PMOS and b) NMOS. The data shows that stress variations account for 40% and 50% of the drain current variance, for PMOS and NMOS, respectively.

Figure 2 (above) shows the correlation between stress and drain current for both PMOS (Fig. 2a) and NMOS (Fig. 2b). The correlation coefficients indicate that stress variations account for 41% (PMOS) and 50% (NMOS) of the drain current variations. The correlations between stress and leakage, drive and drain currents, as well as threshold voltage, are summarized in the table below. All parameters exhibit good correlation, with threshold voltage showing greater sensitivity to factors other than stress.


The data shown in Fig. 2 can be represented in map form, as shown in Figure 3 for PMOS drain current. Figure 3a shows the lot average of the PMOS drain current for the 21 die locations, whereas Fig. 3b shows the lot average of the stress accumulated over multiple steps. Figure 3c shows a plot of this data for reference. Comparison of Figs. 3a and 3b show good agreement and also that the correlation holds for both center and edge die locations. Evaluation of the data across the multiple device parameters indicated that the within-wafer stress variation typically contributes more significantly to device performance variation than wafer-to-wafer variation.

Figure 3. PMOS within wafer variation averaged for a lot of 24 wafers for a) drain current and b) multi-step stress showing good agreement.

A first step toward using stress data for performance optimization is the identification of critical process steps. The extent to which a process is critical can be evaluated by considering three distinct factors. The first factor is the stress non-uniformity of the process, both wafer-to-wafer and within-wafer. The second factor is the stress sensitivity associated with the specific process or more simply, the slope of the device parameter versus stress plot. The third factor is related to the quality of correlation between stress and device performance. In the current case study, the stress variations for each of the 15 steps individually account for a few to several percent of the device performance variance. It is only when multiple steps are considered in combination (typically 5 to 9 steps) that the stress-device performance trends are revealed.

Stress uniformity in advanced annealing

Advanced sub-millisecond annealing processes have the potential to significantly relax stress, as temperatures typically reach >85% the absolute melting temperature of silicon. In the SiGe/Si system, for example, the primary relaxation mechanism involves the formation of interfacial misfit dislocations. The dislocation nucleation rate, ∂N/∂t is given by an exponential relationship: ∂N/∂t ∝ exp(-U/kT), where U is an activation energy, T is absolute temperature and k is Boltzmann’s constant [7]. The exponential dependence has the consequence that misfit dislocation nucleation rate increasingly varies for small temperature fluctuations at increasing nominal temperature. As a result, stress uniformity during advanced annealing is directly related to temperature uniformity, whereas the extent of relaxation is related to the temperature and the time, td (the total number of strain-relaxing misfit dislocations N ~ (∂N/∂t) td).

Therefore, stress management during high temperature annealing is incumbent on temperature control. Figure 4 shows maps of the stress induced by two different millisecond annealing processes: laser spike annealing (LSA) in Fig. 4a, and a lamp-based system in Fig. 4b, on the identical device structure. Comparison of the two stress maps indicates a fundamentally different response: the LSA induced stress (Fig. 4a) is highly uniform, whereas the stress induced by the lamp-based system (Fig. 4b) varies dramatically from locally tensile (red) to compressive (darkest blue). The periodic pattern of the lamp-induced stress map follows precisely the die-layout, indicating a strong pattern dependence of the lamp-based anneal process.

Figure 4. Full-wafer CGS maps of stress induced by millisecond anneal on the identical device: a) LSA-induced stress, b) stress induced by a lamp-based system. The large stress variations induced by the lamp-based system correspond to distinct pattern features and repeat from die-to-die.

The differences in stress can be understood by considering two different sources: a) the inherent characteristics of the technology, and b) process flexibility. Strong pattern effects of the type apparent in Fig. 4b are typically a consequence of the within-wafer or within-die variations in reflectivity [8]. Reflectivity is dependent on the source wavelength and angle of incidence, and consequently is inherent to the specific annealing technology. LSA utilizes a long wavelength infrared source, incident at the Brewster angle which results in relatively low, uniform reflectivity for a broad range of materials [8]. In addition to the inherent pattern insensitivity of LSA, further temperature control is achieved by closed loop feedback [9]. In contrast, the use of normal-incidence shorter wavelengths in the visible spectrum, as in some lamp-based or other laser-based systems can result in large reflectivity variations, causing temperature variations of greater than 100°C in some cases [10].

Beyond the technology-specific attributes, an annealing system can facilitate stress management by providing flexibility to adjust the process. As noted above, the annealing dwell time is directly related to the number of strain-relaxing misfit dislocations generated during annealing in SiGe/Si systems. The dwell time flexibility of the LSA system has been used effectively to reduce stress relaxation in devices incorporating e-SiGe, such that a 50% reduction in dwell time resulted in >3× reduction in lithography mis-alignment [11]. The benefits of low dwell time are not limited to e-SiGe technologies, and have been shown to be effective in managing stress for a variety of device technologies. Lamp-based millisecond annealing systems have limited dwell time flexibility, and hence the only approach to minimize strain relaxation in advanced devices is a reduction in peak temperature. While reducing temperature may minimizes stress effects, it also can substantially limit the performance gains that can be achieved using millisecond anneal: for example, increasing peak temperature by 100°C led to a >5% improvement in drive current in a 65nm nMOS device [11,12].


Advanced technology development will require stress management beyond the scale of the gate length. Stress variations within-die, within-wafer and wafer-to-wafer can cause downstream process issues as well as ultimately affect device performance and yield. Lithography overlay requirements are becoming increasingly stringent for the next-generation devices, and the first case study illustrated the role that stress non-uniformity has in misalignment. The second case study showed that cumulative stress variations in the front-end are related device performance variations measured at the end of line. Stress-related issues fundamentally dictate the integration of advanced annealing. Annealing technologies that inherently offer high thermal uniformity, provide process flexibility and low stress, such as LSA, are essential for enabling stress management at technology nodes beyond 32nm.


David M. Owen received his BS from the U. of California, Berkeley and his MS and PhD from the U. of California, San Diego and is the chief technologist for surface metrology at Ultratech, Inc., 3050 Zanker Rd., San Jose, CA 95134 USA; ph. 408-321-8835; email [email protected].

Jeff Hebb received his BS from the Technical U. of Nova Scotia, and his MS and PhD from the Massachusetts Institute of Technology and is VP of LSA Product Marketing at Ultratech, Inc., 3050 Zanker Rd., San Jose, CA 95134 USA; ph. 408-321-6228; email [email protected].


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