August 25, 2009 – In a bid to “fully utilize” the benefits it can offer customers, Taiwan Semiconductor Manufacturing Co. (TSMC) says it will add a third flavor of its forthcoming 28nm process technology: a low-power high-k metal gate (HK+MG) one. The foundry says it is the first to achieve “functional 64Mb SRAM yield” for any 28nm node, let alone all three flavors.
First tipped in Sept. 2008, TSMC’s 28nm plans (billed as a “full-node” technology, not a shrink) called for two, and now three flavors. A low-power process with silicon oxynitride (SiON) will be first off the line with “risk production,” followed the next quarter by a high-power process using a gate-last high-k metal gate (HK+MG) approach. The newly announced low-power HK+MG process, a derivative of the high-power HK+MG process, will enter “risk production” in 3Q09, offering low power, low leakage, and “medium-high performance,” targeting applications ranging from cell phones to netbooks and other wireless/portable devices.
What’s the difference in the three flavors? The 28nm “LP” (low-power SiON) targets areas “where lower cost and faster time-to-market” are paramount, e.g., some cellular and handheld applications. The 28nm “HP” process (high-power with HK+MG) targets devices like CPUs, GPUs, chipsets, and FPGAs. The “HPL” (low-power with HK+MG) is being marketed as “suitable as a SoC platform for general market applications.”