New cell could extend DRAM scalability improve performance

by Kwok Ng, Semiconductor Research Corp., and T.P. Ma, Yale University

September 29, 2009 – Researchers at Yale University have developed a new DRAM cell using ferroelectric layers that could significantly improve the technological and market competiveness for DRAM technology.

It has been long recognized that the polarization under an electric field in ferroelectric materials has great potential for memory devices. [1] Some degree of success has been achieved in incorporating ferroelectrics in a capacitor in a 1T-1C (1-transistor-1-capacitor) DRAM configuration. However, a capacitor is still needed and imposes severe scaling challenges, so the major limitation has not been removed. There have been many research activities in incorporating ferroelectrics as gate dielectrics in a MOSFET as a single-transistor nonvolatile memory (NVM) cell, but the retention time has never been able to meet the stringent requirement — and industry standard [2] — of 10-year retention time.

These new results aim for the application of DRAM rather than NVM. The advantages compared to standard DRAM include more than three orders-of-magnitude in retention time, so refreshing frequency can be relaxed accordingly. The elimination of the capacitor enables the technology to be much more scalable for nodes beyond ~22nm, which would not be the case for the 1T-1C DRAM cell. Without a large capacitor, the technology is also more compatible with embedded technology. Other advantages include 20× lower dynamic power, non-destructive read, and faster read/write speed.

Classes of common semiconductor memories

The major semiconductor memories are (1) NVM, (2) SRAM, and (3) DRAM, each with advantages and limitations. NVM is able to retain data even after power is off, and its high density is attractive for mass storage such as video (motion and still) and audio recording. NVM’s limitations are writing speed and endurance. SRAM is a latch or flip-flop that retains the data as long as the power is on. It has fast operation, but the penalty is the large area per cell that typically consists of six transistors each. DRAM has the advantages of fast operation and a reasonably small footprint of 1T-1C, but the retention time is the shortest in the order of 10msec; because of that, data needs to be refreshed periodically to not be totally lost.

An ideal memory should have the properties of (1) long retention (nonvolatility), (2) small footprint with long-term scalability and (3) fast operation. For NVM, improving the operation speed would be highly desirable but difficult. The large cell area of SRAM is a more fundamental problem, and a completely different device concept would be needed if major improvement is to be realized. For DRAM, improving the scalability by possibly eliminating the capacitor and improving the retention time would be major steps. The newly proposed FeDRAM cell presents these two major improvements, along with other advantages.

It has to be clarified that in literature, some DRAM cells made on SOI substrate are referred to as being 1T cells. This is because the transistor body-to-substrate capacitance is used as the equivalent storage capacitor in place of a trench capacitor or stacked capacitor. This design eliminates the need for added layout area, but the fundamental problem of retention time of a 1T-1C cell is still present.

Background of FeRAM

Currently in commercial products, the only ferroelectric RAMs are ones where the ferroelectrics are used in the capacitor of the 1T-1C structures. The operation of this design is different from a conventional DRAM cell in that the memory state is the polarization within the dielectrics, rather than charge across the capacitor. The cell is read by sensing the displacement current when applying a voltage pulse, rather than sensing the amount of charge directly. Because of this property, the memory is more stable. It requires refreshing only after reading. However, the drawback remains of requiring a large-area capacitor.

Working principles of FeDRAM

The structure of the FeDRAM transistor cell is simply a MOSFET with ferroelectrics as the gate dielectrics. Its programming and erasing are demonstrated by the schematic drawings in Figure 1. When a positive voltage pulse is applied to the gate (Fig. 1a), the ferroelectric responds by internal polarization as dipoles. After the applied voltage is removed, this internal polarization remains as a built-in internal field that changes the threshold voltage of the transistor. When a pulse of the opposite polarity is applied to the gate, the polarization is reversed, again changing the threshold voltage of the transistor (Fig. 1b). By detecting the current of the transistor, the threshold voltage is known, and the state of the memory is known. Note that this read scheme is identical to that of the nonvolatile flash memory, and that it is non-destructive so one can read many times without refreshing.

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Figure 1. Operation principle of FeDRAM during (a) programming and (b) erasing.

The details of the ferroelectric effect are shown in Figure 2 (a). Here the internal field E is proportional to the applied gate bias, and the polarization P is the internal dipoles built up within the ferroelectrics. The hysteresis depends on the direction of the applied field, and is the main feature contributing to the memory effect. The same effect is manifested in the transistor I-V characteristics shown in Fig. 2b. Note that the I-V characteristics can be much sharper than the P-E plot.

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Figure 2. (a) Hysteresis of P-E relationship in ferroelectrics gives rise to that in (b) MOSFET Id -Vg characteristics.

The characteristics in Fig. 2 are time-dependent, on both the ramping rate of the applied gate voltage as well as the time after the bias is taken off. The latter, known as the retention time in memory applications, is depicted in Figure 3 after either programming or erasing. It is shown that the retention time is in the order of minutes — not enough for nonvolatile memory, but a big improvement over current DRAM capability, by more than three orders-of-magnitude. The retention time in the device is limited by the depolarization field and trapping of carriers when electrons tunnel through the gate dielectrics at zero bias. Both the depolarization field and the tunneling current are caused by the internal field built up from polarization. The gate stack consists of the ferroelectrics plus an insulator with higher barrier. The barrier serves to minimize the tunneling current, but at the same time increases the depolarization field, so there is a trade-off when varying the insulator thickness.

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Figure 3. Data retention after programming and erasing biases are taken off.

A more stringent requirement for DRAM than nonvolatile memory is the endurance/reliability of repeated program/erase cycling. The endurance data are shown in Figure 4. The endurance performance is much better than current flash technologies which are mainly floating-gate or charge-trapping types of devices. Both of these devices involve tunneling or hot-carrier emission of electrons through the gate dielectrics, and their endurance is inferior to that of the FeDRAM. As a reference, the industry requirement for nonvolatile memory is 105 cycles — the endurance data shown here are much longer.

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Figure 4. Cycle endurance in FeDRAM exceeds studied measurement range. V and V+ are threshold voltages after program and erase.

Advantages of FeDRAM

There are several advantages of FeDRAM compared to current DRAM technology. Longer retention time requires less frequent refreshing. The elimination of the capacitor enables the cell structure to require a much smaller footprint; cell size of 4F2 has been designed in NOR and AND arrays. This makes the structure more scalable beyond the 20nm node and more compatible to an embedded technology. Because during programming and erasing there is no current involved to charge a capacitor, the dynamic power has been estimated to be 20× smaller. Other advantages include non-destructive reading and up to 8× programming/erasing speed.

Further development

Yale University continues to develop the FeDRAM technology toward commercial realization in cooperation with SRC sponsoring companies, focusing on a more scaled device in channel length beyond the demonstrated ~1μm dimension and in ferroelectric thickness to reduce the programming/erasing voltage. Currently the gate stacks consist of ~200nm of ferroelectrics (PZT [PbZrTiO] or SBT [SrBiTaO]) plus a few nanometers of SiON insulator layer, with dielectric constants of 400, 150, and 7 respectively. The goal is to reduce the operating voltage to be around 1V. Further improvement of retention time is possible with a sharper P-E loop by exploring single-crystalline, single-domain ferroelectrics. Even though programming and erasing speed is already better than that of DRAM, further development would reduce it toward the theoretical value of ~70ps by optimizing the FeDRAM gate stack, minimizing the contact resistance, and minimizing the parasitic RC components. The issues of reliability and variability associated with ferroelectrics need to be examined with a larger pool of statistical data. For a long-term goal, expansion to multi-level or multi-bit architecture would open up a new paradigm for DRAM operation and technology.


Dr. Kwok Ng is Director of Device Sciences at Semiconductor Research Corp. (SRC). E-mail: [email protected],
Dr. T.P. Ma is Raymond John Wean Professor of Electrical Engineering at Yale University.


[1] S. L. Miller and P.J. McWhorter, "Physics of the ferroelectric non-volatile memory field effect transistor," J. Appl. Phys., vol. 72, no. 12, pp. 5999-6010, 1992.

[2] H. Ishiwara, "Current status and prospects of FET-type ferroelectric memories," J. Semicond. Technol. Sci., vol. 1, pp. 1-14, March 2001.


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