October 23, 2009 – The SOI Industry Consortium has released results from a study comparing silicon-on-insulator (SOI) and bulk finFETs, determining that cost and performance are "for all practical purposes equivalent," but finFETs are more challenging to manufacture due to increased process variability.

Three-dimensional finFET designs — which rely on thin verticial silicon "fins" to control current leakage through the transistor in an "off" state — are being explored as a transition from planar CMOS transistors at the 22nm node, because they offer improved channel control and reduced short-channel effects.

SOI used in finFET fabrication uses a buried oxide layer as an etch-stop and isolates individual transistors (fin heights are a function of substrate thickness), and enable better control of fin height and width, the consortium noted — bulk finFETs varied between 150%-160% more than the SOI equivalents, which can lead to "significant end-product variability," the group notes.

"This is a very important study. As the industry contemplates transitioning to non-planar transistors, it is vital to bring the best technical assessments possible of manufacturability, cost and performance between the two substrate options: bulk and SOI," noted Horacio Mendez, executive director of the SOI Industry Consortium, in a statement.

[Editor’s note: A more detailed analysis of the study’s findings of SOI vs. bulk finFETs is featured in SST‘s November issue.]