HP’s Stan Williams: Hybrid CMOS-memristors, the future of analog

by Debra Vogler, senior technical editor, Solid State Technology

November 30, 2009 – Industry luminaries packed the room during the Silicon Valley Engineering Council open house event (Nov. 10 at SEMI’s Global headquarters in San Jose, CA) for keynote speaker Stan Williams, senior Fellow and director of Hewlett Packard’s information & quantum systems lab. He discussed research done by his group on memristors, and summarized the history of research and observations made by others regarding this fourth fundamental circuit element — and he also hinted at upcoming developments to be published soon.

A memristor is the fourth fundamental circuit element (resistor, capacitor, and inductor being the three other well-known circuit elements) that can be described using two equations: a quasi-static equation, and a dynamical equation. The memristor’s properties, Williams explained, depend on time; the state variable depends on the device’s past history. The consequences of these properties and characteristics are that the device’s C-V characteristic curve is a pinched hysteresis loop; the voltage and current always have to be 0 at the same time, so the device cannot store charge or energy, but it can store information. "This is key and profound in terms of being able to build new types of electronic circuits," observed Williams.

Moving Moore’s Law forward, using fewer transistors

The reason memristors join the familiar LCR elements as fundamental is because no combination of LCR circuit elements can be put together to obtain an equivalent circuit that achieves the C-V characteristic curve of the memristor. "These set of four devices (L, C, R and the memristor) form a complete set of functions that can be used to synthesize a wide variety of functions for electronics circuits," explained Williams. Circuit designers have had to build circuits without memristors, but it required a lot of transistors — "It takes an equivalent circuit made up of 15 transistors and 3 capacitors to emulate a single memristor," he noted. With a true memristor, electronic circuitry can be greatly simplified, he explained — essentially decreasing the transistor count by a significant fraction, and in some circuits maybe by an order-of-magnitude. "That’s an interesting way of moving Moore’s Law forward," he observed — "not by getting more functionality by making the transistor smaller, but getting the same functionality by using fewer transistors to achieve the same ends."

Developing a physical model of the memristor

Williams developed a physical model that describes a memristor: two variable resistors in series, one representing the resistance of the doped material (comprising the memristor) and the other the resistance of the undoped material (comprising the memristor). "A memristor causes the relative sizes of the two resistances to change in such a way that the drift velocity of oxygen vacancies equals the mobility of the oxygen vacancies times the electric field in the device — an equation derived by Steve Kang," explained Williams. Solving the device equations finds that memristance is proportional to 1/D2, where D is the width of the device. "So at the nanometer scale of a device, memristance is one million times more important than at the micron scale, and at the millimeter scale, it’s completely negligible," Williams noted. This explains why it’s only recently, as the industry makes much smaller devices, that memristance is being observed. "Drift velocity and electric field in devices are getting so large that the effect is not only noticeable, but in some cases prominent […] people are seeing hysteresis in their circuits that’s unexpected," he said. It’s not stray capacitance or inductance, but rather memristance. "Very small circuits in which potential is turned on and they [researchers] are starting to move atoms around in devices as well as electrons and holes."

Because memristors are dynamic devices (dependent on their past history), Williams said that they can’t be measured using a curve tracer, though many have tried to do it. A curve tracer’s software will perform an integration to get some level of signal-to-noise — but as it’s doing so, the resistance of the device is changing, "so a memristor will drive the curve tracer crazy where I-V characteristics appear to oscillate," he observed. It’s gotten to the point, he lightheartedly observed, where HP researchers can look at a paper and tell which model/brand of curve tracer was used to collect data. "The older the curve tracer, the better the results," he said, "because it has less software."

Instead of using a curve tracer, a memristor’s state needs to be measured using a pulse-probe type of experiment, explained Williams, whereby a very small triangular saw-tooth wave (both negative and positive) and then a pulse are applied to the device. The pulse widths are increased incrementally exponentially (1μsec to ~10sec); after each pulse, the state of the device is determined. Because memristors are tunneling devices, the state at any given point in time is determined by the width of the tunneling barrier. By fitting hundreds of I-V characteristic curves and comparing them at various points in time, the width of the tunneling barrier — at any point in time — can be determined. Plotting over a wide variety of times and applied bias voltages obtains a set of curves that shows how the device turns off and how it turns back on, noted Williams. "The result is a state equation to tell you how the device evolves in time with voltage."

Describing an empirical model of the device, Williams explained that a conducting channel (or conducting pillar) almost bridges the gap between two platinum electrodes, leaving a 2nm-wide tunnel barrier at the top of the conduction channel. As voltage is applied, oxygen vacancies are driven out of the conduction channel into the barrier region, which changes the resistance of the device. The diffusion constant for the oxygen vacancies is practically zero, so in the absence of an applied bias voltage, nothing happens — i.e., "data stored will be there as long as we will be here," he noted. To erase the data, one simply inverts the polarity. HP researchers were able to predict the existence of the conduction channel using electrical measurements fitted to I-V characteristics, and verified its existence after peeling off a top electrode and examining the device with an AFM.

A CMOS-memristor hybrid

HP has now developed a device that can be operated as either a memristor or a memistor, depending on whether or not it is operated as a 2-terminal or a 3-terminal device (based on how the bias voltage is applied). The device itself is a 30nm wide (5nm active region) single structure that can be utilized as three different memristors when operated as a 2-terminal device, or operated as a single 3-terminal memistor. Results will be published soon, Williams promised, with the intentions to be able to build analog computers someday.

Williams’ research group has built a hybrid CMOS-memristor chip — using an inkjet CMOS process at a foundry that makes HP inkjet technology — developing all the processing techniques required to integrate memristors and memistors with transistors in a circuit. "From this platform, we hope to launch a number of new technologies for memory" (e.g., replacing flash memory storage), "and when we get giddy, we hope to replace DRAM, SRAM, magnetic card disks, DVDs, CDs, and so forth," said Williams. "We’re also looking at doing away with Boolean logic — i.e., using synaptic computing," based on the analog difference in the junctions of the device. The challenge, he said, is to monitor the processes in the region between the conducting channel and the top electrode, essentially watching switching in real time.

The aforementioned hybrid CMOS-memristor had 100nm memristor features, but the intent of using the inkjet process was to demonstrate the process compatibility as well as to show that different generations of feature sizes could be used with respect to CMOS and the memristors, Williams pointed out. "What we’re looking to do is to continually shrink memristors to smaller and smaller sizes long after people stop trying to shrink CMOS," he said. "We think that you can make very capable circuits with 45nm CMOS for example, but then integrate maybe even 5nm memristors on top of that — a combination that is very interesting for both storage and computation."


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