Mentor tips plans for unified Si test, yield analysis

November 3, 2009 – Mentor Graphics is launching what it calls a comprehensive test and yield analysis platform incorporating homegrown and acquired technologies, to help customers drill down through failure analysis data to better identify defects and fix them, thus saving time and improving yields.

The unification plan combines Mentor’s embedded compression and automatic test pattern generation (ATPG) technology with the built-in self-test (BIST) technology (for memory and logic) it acquired through LogicVision in May 2009. The new product line, Tessent, combines a Diagnosis tool for automated scan test failure collection and diagnosis, and a new YieldInsight product to analyzed/visualize and drill-down through large volumes of production test failure diagnosis data. Other facets of the Tessent suite include silicon debug/characterization (LogicVision’s SiliconInsight product) and layout-aware diagnosis (Mentor’s tools).

The Diagnosis software performs volume diagnosis of manufacturing test failures (based on FastScan or TestKompress scan patterns), providing information beyond single-device defect location to classify all major defect mechanisms, and use layout information to identify physical features and cell types associated with a defect type (e.g., attributes ranging from via type to metal layer and failing scan cells). Diagnosis results are compared to expected distribution to help spot patterns in the failure diagnosis data that might point to systematic issues. Further analysis helps understand the impact of each systematic problem and helps select devices for physical failure analysis that clearly exhibit the identified problem; this raises analysis success rate, and reduces time needed to verify root causes.

An example the company gave in a presentation describes a customer that performed signature analysis on failure diagnosis data, indicating a systematic issue contributed to yield loss, which was further identified as defects associated with a specific single defective via on layer 5; a manufacturing process change was made to correct the issue and eliminate future yield excursions.

"For the first time in the industry we are really closing the design-to-silicon loop by extracting statistical information from silicon test failure data and using it to identify precisely where in the design or manufacturing process we can best impact yield and quality," stated Joseph Sawicki, VP/GM of Mentor’s design-to-silicon division. "The combination of Mentor’s market-leading scan-based test and yield analysis products, and the LogicVision BIST solutions, puts us in the top spot across the board in silicon test," he proclaimed.

In a statement, Mentor cited feedback from yearlong customer TSMC, which said Mentor’s failure diagnosis tools have "accurately diagnose[d] failing die and can effectively pin-point problem areas within the die, even when the problem is internal to a cell, which is very important for physical failure analysis," said Shauh-Teh Juang, senior director of design infrastructure marketing at the foundry, in a statement. The company also noted comments from customer STMicroelectronics, which said YieldInsight allowed them to "identify yield issues in days, as well as determining the impact of process modifications by carefully examining the failure signatures."

Going forward, Mentor’s BIST offerings will be based on the former LogicVision platform, and test-pattern generation will be based on Mentor’s TestKompress and FastScan platform; some of Mentor’s former BIST products, and LogicVision’s ATPG products, will be discontinued, though support will be offered during a transition to the new ones. Mentor said it also will invest and develop mixed-signal BIST technologies for Serdes and PLL testing as well as LogicVision’s SiliconInsight line, and will seek to add more functionality to the Tessent line for "emerging challenges related to test."


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