Speaking at the International Electron Devices Meeting (IEDM) in Baltimore, IMEC’s Thomas Hoffman outlined challenges and possible options of high-k metal-gate (HKMG) transistor stack materials and processes for future device generations. He compared gate-first and gate-last advantages and disadvantages, the role of HKMG in advanced 3D transistor structures, such as the FinFET our tri-gate transistor, possible options to fix flatband roll-off problems, and an intriguing solution involving channel engineering with silicon germanium (SiGe). Hoffman provided his analysis during a short course session on Sunday.

Hoffman said that what had become the standard material for the transistor gate dielectric — silicon oxynitride (SiON) – ran out of steam at the 90nm node. Films could not be made much thinner than 11-12Å without creating excessive leakage current. The alternative is a high-k dielectric, such as HfO₂, which can reduce gate leakage by orders of magnitude. "With this new material we are able to sustain Moore’s Law," Hoffman said. "It not only fixes the leakage problem but allows scaling to continue." Due to compatibility issues with standard polysilicon gates revolving around defects that cause "Fermi pinning" which prevents transistors from switching properly at low threshold voltages, high-k gate dielectrics must be paired with a metal gate electrode. "These defects in the bandgap prevent gate voltage swing. The end result is a high V_t," Hoffman said. An added advantage of metal gates is that a common reliability problem — polysilicon depletion — is suppressed.

High-k has many challenging material requirements, particularly with thermal stability, morphology and interface quality, Hoffman noted — thermal stability is typically poor, and films can be deposited with an amorphous morphology but then crystallize at higher temperatures. The conformality and topography of the deposition method are also critical, especially "as we move to 3D devices such as the FinFET," he said. Hafnium silicates provide "slightly better thermal stability" than HfO₂, he said, but at the expense of a lower k value. Nitrided hafnium silicates are a good compromise, he noted, and they could probably be used for the next device generation. Hf-Al-O offers a wide range of k-values, but needs more work to be put into production.

The secret in successfully implementing HKMG, Hoffman said, is in finding a way to tune the threshold voltage (V_t) for both PMOS and NMOS transistors: "that’s where things start to get complicated." One way is through capping layers in between the high-k and metal or between an interlevel dielectric (which sits atop the channel region) and the high-k material. Al₂O₃ and La₂O₃ are example of capping layer materials that have been extensively reported. Hoffman said that with the Al₂O₃ process, which is thermally activated, "you can form dipoles which set the desired workfunction."

High-k first, gate-last structure. (Source: Hoffman/IMEC, IEDM 2009; acknowledgement C. Auth, VLSI ’08)

Another approach to V_t tuning is to select an electrode material with the desired work function. Many candidate materials with different work functions have been proposed and researched, but Hoffman said "there doesn’t seem to be much consolidation." Candidates include TaN, TiN and TaSiN, some films with "richer" mixtures of Ta or N. One reason there has not been consolidation is that most metals tend to migrate towards midgap work functions after high-temperature anneals. For this approach to work then, it’s important for metal to not be exposed to high temperatures, and the only way to do that is with a gate-last process strategy (sometimes called gate replacement or "cold flow" process).

In a gate-last process, the high-k material is deposited dummy gates are created, followed by source/drain formation and an interlevel dielectric (ILD) deposition and polish. The dummy gates are removed and different workfuction metals are deposited for NMOS and PMOS.

Companies that have reported on a gate-first process include IBM, UMC, Panasonic, Renesas, while gate-last processes have been reported by Intel and TSMC. Hoffman said a third approach, full silicidation (FUSI), where a polysilicon gate is totally converted to a silicide, has been abandoned due to a too-narrow process window.

An interesting alternative described by Hoffman that achieves high V_t with scaled effective oxide thickness for PMOS is channel engineering. He said a SiGe channel process would allow gate-first process strategy, and would require only one capping layer instead of two.

An on-going problem with HKMG, first reported by SEMATECH, is flat-band voltage roll-off. "As the flat-band voltage is rolling off, the PMOS Vt is going up again," Hoffman said. This problem is caused by oxygen vacancies/defects in the high-k material, which can diffuse and interlayer growth. There are two approaches to solving this problem, he noted. Since it’s a thermally activated issue, going to lower or neutral thermal budgets would help. This might mean going from a spike anneal, for example, to a laser anneal. The second solution is to passivate by oxygenation, either lateral oxygenation after source/drain activation, or oxygenation through a thin layer of TiN (Hoffman referenced work by Cartier, from VLSI ’09 and APL, vol. 95, 2009).

Hoffman said that nobody has disclosed anything yet for the 22nm node, although he said that HKMG would have a role for 3D types of devices such as the FinFET.