December 14, 2009 – Researchers at Stanford disclosed their latest work at this year’s International Electron Devices Meeting (IEDM) on combining carbon nanotubes (CNT) and logic circuits to devise new techniques for preventing flaws and building multilayer chip prototypes. The transistors are said to be grouped in the same "cascading" sequences as for computational logic and memory, with processes compatible with standard industrial-scale VLSI (very large scale integration) manufacturing.
"Carbon nanotube transistor technology has moved beyond the realm of scientific discovery and into engineering research," stated H.-S. Philip Wong, professor of electrical engineering at Stanford and a co-author of the paper. "We are now able to construct devices and build circuits on a wafer scale as opposed to previous ‘one-of-a-kind’ type demonstrations."
The chips employ two techniques already developed at Stanford: one (invented in 2007) to enable working transistors regardless of whether the CNTs are straight, and another (invented in 2008) to enable VLSI-scale fabrication of nanotube transistors on a chip. A third, newly developed technique announced at this year’s IEDM is a process for reliable removal of "metallic" CNTs that can conduct electrical current and short-circuit transistors. This technique, dubbed "VLSI-compatible metallic nanotube removal" (VMR), makes practical a previous idea (from Paul Collins and IBM colleagues, circa 2001) to break up the CNTs by exposing them to light, by creating a grid of electrodes to "zap" them away; this same grid can then be etched to produce any circuit design.
An electron microscope image showing carbon nanotube transistors (CNTs) arranged in an integrated logic circuit. (Source: Stanford)
Another IEDM disclosure from Stanford follows up on the VMR work by creating the first multilayer CNT 3D integrated circuit. 3D circuits are already being stacked and connected with conventional chipmaking materials, but the new research shows it can be done with CNTs integrated from the start as a 3D design that yields a higher density of connections among the layers. A prototype three-layer chip with dozens of CNT transistors were connected in functioning gates by nanotube and metal wiring — key to the achievement was a "relatively low-temperature process" that transfers CNTs from a quartz wafer onto a silicon chip.
Still a challenge is to increase the number of CNTs that can be patterned onto a given area on the chip, to thus scale up to modern chip design complexity of millions of transistors. The Semiconductor Research Corporation’s Focus Center Research Program and the National Science Foundation helped fund the research.