February 15, 2010 –  Last week’s IEEE International Solid-State Circuits Conference 2010 (ISSCC, Feb. 7-11, San Francisco, CA), offered many talks and papers on topics ranging from 3D integration to circuit design and memories. Here’s just a few examples.

A forum on silicon 3D integration, bringing together 3D integration technologies including system-in-package, through-silicon via (TSV), and contactless chip-to-chip communication, with an eye toward various components (SDRAM, flash, SoC, sensors, etc.) and applications (imagers, smart phones, solid-state drives, etc.). Among the takeaways, as reported to SST/AP by IMEC‘s Pol Marchal, senior research in 3D integration:

– 3D technology is reaching maturity, but the design community still must pathfind opportunities; a "minimum hurdle" needs to be taken — most likely in memory or a mobile application where improved formfactor and power reductions by reengineering the DRAM interface "make lots of sense." Thermal challenges are also less.

– Reliability, especially in chip-package interation, is also a key concern for 3D. The different materials in the stack, bumps, underfill materials, and thin silicon dies with extreme low-k BEOL narrow design windows. (IMEC is active in this field with R&D and characterization through test chips, working with partners to put in place solutions for reliable systems, Marchal notes.)


Marchal et al. from IMEC had a separate presentation (paper 7.8) in which they offered ideas on design considerations for low-cost 3D through-silicon via (TSV) technologies, enabling applications such as logic-on-logic, DRAM-on-logic, and RF-on-logic. The TSVs were fabricated (5μm dia., 10μm minimum pitch) in 200mm/130 nmCMOS logic with Cu/SiO₂ BEOL; after etching the TSVs, an isolation layer was deposited followed by Cu metallization and then standard BEOL process. The wafers were thinned to ~25μm and next TSVs exposed to height ~700nm, wafers were diced and stacked face-up on a regular thickness landing wafer win a die-to-wafer approach, reducing cycle time (by parallel processing of Cu-Cu thermocompression) and reducing overall cost since the die-to-wafer configuration enables pre-stacking selection of known good die.

Among findings after examining TSV formation and testing:

– Models and tools to design for TSV impact on devices can avoid large keep-out areas (in which no devices are placed) and keep down costs;
– Adding BEOL structures such as vias and serpentine wires next to/on top of TSVs help detect reliability problems;
– Unless power dissipation is managed across the tiers in a 3D stack, hot spots may occur (due to reduced thermal spreading and poorly conductive adhesives). Power dissipation was shown to be ~3x higher max temperature increase than 2D, requiring thermal-aware floorplanning to avoid thermal problems in the stack;
– Protecting TSVs from ESD would increase the footprint of 3D connections and thus cost — but in this presented technology, no ESD was required.
– Substrate noise isolation between stacked tiers was superior vs. 2D, seen as beneficial for mixed-signal and RF applications;
– Additional challenges include design-for-test and packaging of the 3D chip stacks, as well as further reliability testing.

Other ISSCC papers of note

Besides its work in 3D integration/TSV, IMEC had a bushel of other papers at ISSCC: including:

– Intel presented a handful of papers with the emphasis on its 32nm "Westmere" processors, But several of its themes also crossed over into the packaging arena as well. Paper 8.1 ("A 47×~10Gb/s 1.4mW/(Gb/s) Parallel Interface in 45nm CMOS," F. O’Mahony et. al.) described a chip-to-chip interface for future components (processors, memory, and peripherals) featuring a dense interconnect topology that promises to greatly reduce power — the promise is for 10× better power efficiency in data chip-to-chip than what’s available today.

Two components are on packages with interconnect between them, explained Randy Mooney, Intel Fellow and director of Intel Labs’ I/O Research. Key to this achievement is a "different style of interconnect," he said; traditionally they go from the chip down to the motherboard and across to the other die; in this case, the chip is connected directly off the top of the package it’s mounted on, and into the chip in the adjacent package with which it communicates.

As a theoretical example, he envisioned a future terascale processor needing to move a terabyte/sec of data between chips. Using today’s interconnect and I/O, that would require "on the order of 150W — tremendous power" just for the I/O," he said. With this new interconnect scheme, that can be cut to just 11W.

Another Intel paper discussed a prototype of a "universal" transceiver for system I/O (paper 20.7, "A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) Reconfigurable Transceiver in 45 nmCMOS"), with the ultimate goal to "potentially build a single I/O for many applications," noted Mooney. He explained that this technology adopts a scheme to adapt the transceiver to either system configuration or operating configuration to operate optimally, across a very wide range (5-25gbit/signal), and choosing the method of sending data between chips. Mooney pointed out the various options with this technology, including chip-chip, package-package, or board-board, copper, and even optical interconnects.

– Fujitsu had several ISSCC papers:
1) A read-method for spin-torque-transfer MRAM, developed with the U. of Toronto, that solves a problem of erroneous writes during read operations (paper 14.1);
2) Also with the U. of Toronto, a new gigabit-class high-speed transceiver chip with digital circuitry instead of analog-circuit structures, cutting development periods in half (paper 8.7);
3) New frequency synthesizers in 65nm CMOS designed specifically for tuners for terrestrial digital TVs, reducing circuit size by two-thirds and eliminating the need for external components such as external filters

– Sony showed a millimeter-wave wireless intraconnection technology for internal high-speed data transfer, replacing wires and internal circuitry — specifically, integrating millimeter-wave circuits on 40nm CMOS LSIs (0.13mm2 total active footprint)