Seiko Instruments, IME develop Si-based resonator, wafer-level packaging tech

March 17, 2010 – Seiko Instruments Inc. (SII) and the Institute of Microelectronics (IME) of Singapore’s Agency for Science, Technology and Research (A*STAR) say they have developed a high-precision silicon-based MEMS resonator [PDF link] that they say solves a key problem with such devices, to help ensure precise output frequency and enable low-power consumption and miniaturization. They’ve also devices a new wafer-level packaging technology that improves the mechanical strength and lowers fabrication cost.

Benefits of silicon-based MEMS resonators vs. quartz crystals is threefold: integration with CMOS, ideally lower costs, and standardized IC packaging — which will enable not just the use of low-profile packaging, but also the use of standardized IC pick-and-place assembly equipment.

Due to several factors (e.g. thermal expansion and Young’s modulus), silicon-based resonators pose a challenge: resonant frequency fluctuates with temperature changes, generally with coefficient of -40ppm/°C. In other words, for an operating temperature limit of -40°C to 80°C, the resonant frequency will fluctuate ~5000ppm, which makes it very difficult to ensure precise output frequency in the resonator, the companies point out. An electrical circuit can compensate for these changes, but that creates problems in designing low-power consumption and miniaturization, and generates noise in the output.

Figure 1. Microscopic image of the developed silicon resonator. (Source: SII, IME)

Their answer: add a layer of silicon dioxide film to the MEMS resonator, fabricated on a silicon-on-insulator (SOI) substrate, and with a structure that produces residual stress within the resonator (Figure 1).

The new device improves temperature coefficient of resonant frequency fluctuation from -40ppm/°C to +-2ppm/°C, and controls frequency accuracy to a range within max. 500pm at operating temperatures (Figures 2 & 3). This reduces the need for temperature compensation to the minimal, and allows for application in low power consuming, miniaturized, and high-precision resonator.

Figure 2. Thermal properties of commonly used silicon resonator (Source: SII, IME)

Figure 3. Thermal properties of developed silicon resonator (Source: SII, IME)

New wafer-level packaging for vacuum-sealing MEMS devices

As part of their work in MEMS resonators, SII and IME have pushed ahead with a research project begun in 2007: development of a vacuum-sealing process technology for MEMS devices. A vacuum environment (typically anodic bonding) is used for sealing processes for MEMS devices such as resonators with silicon substrates — but is limited to high-temperatures (400°C~500°C)

and voltages (600~1000V) which can cause warping. Moreover, getters need to be added during sealing to remove gases (e.g. oxygen) produced during the vacuum packaging process.

To fix this, SII and IME have come up with a gold-tin eutectic bonding process, that can take place at temperatures low enough to inhibit release of gases during bonding; thus a higher level of vacuum sealing (<26Pa) can be achieved without using getters, and an external electrode can be drawn out laterally without passing through the substrate. This method improves mechanical strength, and also lowers fabrication costs.

Figure 4. Cross-section of vacuum package with gold-tin eutectic bonding. (Source: SII, IME)

The combined MEMS resonator and new wafer-level packing (WLP) technology have been "successfully tested," and SII plans to further evaluate their performance to verify possibility of a miniaturized, low-power-consumption resonator. Application would be in high-frequency resonators (instead of quartz crystals), enabling low-cost, high-mix low-volume production and miniaturized single-chip high-frequency resonators.


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.