Vage Oganesian of Tessera and Vern Solberg, Tessera consultant, discuss the advanced packaging options available with 3D contact features on substrate interposers for complex, high-pin-count flip chip applications.

The electronics industry has acknowledged that increases in semiconductor circuit density pose interconnect challenges for the packaged chip’s thermal, mechanical, and electrical integrity. Although the majority of available semiconductors continue to use wire bond package construction, manufacturers of more complex and higher performance products have opted for a substrate-based array configured packaging. By utilizing a uniform array of contact features, the substrate interposer can enable smaller contact pitch, improve electrical path integrity, enhance reliability performance and minimize the finished package outline.

Figure 1. Build-up substrate with solid copper filled micro-via.

Consistent die-to-substrate interface with decreased  contact pitch or spacing allows far greater contact density and enables shorter electrical path lengths. A shorter conductor path reduces inductance and, because the contacts are directly beneath the die element, heat dissipation is better facilitated through the substrate interconnects to the host circuit structure. These characteristics make the array package suitable for various devices: microprocessors, microcontrollers, ASICs, memory, PC chip sets, and other products. Substrate fabrication for semiconductor packaging is a somewhat specialized segment of the electronics industry. This is due in part to its unique requirements for high circuit density, enhanced electrical performance and thermal stability. A laminate substrate designed for array packaging, for example, may have one, two, or several circuit layers, especially for the higher I/O semiconductor applications. Several organic substrate compositions are furnished with a relatively high glass transition temperature (T_g), provide a low dielectric constant, and exhibit excellent insulation properties. Materials have also been developed to provide improved high frequency (HF) performance while maintaining the ease of fabrication associated with commercial epoxy/glass laminates. The material is described as reinforced woven glass with a ceramic-filled thermoset material. This specialized material combination furnishes a very high T_g (>280°C), which can meet high thermal operating condition requirements.

Substrates for semiconductor packaging can be furnished with several routing layers and there are a number of methods for integrating passive devices within these layers. To meet system-level performance and density requirements, the finished semiconductor packaging must provide thermal and electrical characteristics that will enhance performance of the die element. New advanced packaging technologies must also consider the ever-increasing market demand for smaller size, more I/Os and minimized package cost. Substrate cost is greatly influenced by the materials specified, the number of circuit layers, and routing complexity. When two or more circuit layers are needed, the metal planes or traces are interconnected to each other by plated through-hole (PTH) or partially formed vias, in the same way as conventional PCBs used for second-level assembly. Although packaging less complex semiconductors may require only one or two metal layers, the higher I/O and high-performance semiconductors will need additional layers for in-package circuit routing and power and ground distribution. For example, a substrate construction with two build-up circuit layers on each side of a two-layer core (2-2-2) will typically employ semi-additive patterning for the high-definition build-up circuit pattern and subtractive patterning for the core or base layers of the substrate. The inner and outer circuit layers are most commonly connected through laser ablated and plated via holes. To better facilitate higher density circuit routing for the semiconductor element, the industry has adopted via-in-pad techniques using laser ablated and plated micro-vias (Figure 1). As functionality increases, wiring density also needs to increase. Filling of blind micro-vias with copper, initially developed to accommodate high-density semiconductor substrate applications, is currently in wide use for build-up circuit boards developed for wireless handsets with very high component density.

The demand for a greater number of functions on a single chip requires the integration of an increased number of transistors or bits for each product generation. Typically, the number of pads and pins necessary to allow I/O signals to flow to and from an integrated circuit increases as the number of transistors on a chip increases. While a number of semiconductor package substrates require only 2 or 4 layers of build-up, substrate production with increased layer count is on the rise. Several substrate suppliers are expected to implement 10- to 14-layer substrates for 45-nm devices in the near term. Intel’s Presler 65-nm processor, for example, was introduced with a 12-layer substrate and the company’s 45-nm Atom processor uses a 6-layer substrate. Sun Microsystems, a company that traditionally used ceramic substrates for its high-performance semiconductors, reports that increases in layer count make lower-cost organic substrates an attractive alternative for some of its new microprocessors.

Materials development is an important underpinning of most technology advances. Industry roadmaps consistently point to materials and process refinement as key enablers for new technologies, improving product performance and manufacturing efficiency. In addition, product developers have realized that wire-bond die-to-substrate interface does not always meet optimum performance criteria for all applications, especially for the growing number of higher-speed processor and ASIC products noted previously. For the next generations of products, the semiconductor suppliers have abandoned traditional wire-bond package assembly methods altogether, opting instead for the more compact die-face-down flip-chip (FC) attachment methodology. There are issues, however, that may impede defect-free joining of the high-density flip-chip die, solder bump uniformity, and substrate flatness.

Electromigration in very-fine-pitch flip-chip applications can contribute to the formation of intermetallic compounds that, over time, can form a conductive bridge between closely space contact features. The effect can be catastrophic in flip-chip applications where high direct current densities are used. As the structure size of the die element decreases, the significance of this effect increases.

Figure 2. High-density flip chip mounted onto a µPILR configured substrate.

A potential solution for high-density flip-chip mounting is a relatively new build-up substrate fabrication process that was developed to provide an array of uniform raised contact features that have proved ideal for bumped die mounting (Figure 2). The raised contacts* are formed using a subtractive process during the final stage of the package substrate fabrication process. The raised contact features provide a uniform planar package interconnect, meeting the requirements of very-fine-pitch and high-pin-count flip-chip-configured die elements. This technology is designed to eliminate solder printing on the package substrate, allowing high yields at bump pitches of 150 µm or less. The system also enables high aspect ratio connections and positive stand-off height for underfill flow control even with low melt solders. The raised contact substrate allows designers to provide finer bump pitch on the die without reducing pad size that may contribute to current crowding and electromigration problems.

*The raised contacts formed are trademarked µPILR.

Vage Oganesian, VP, R&D, Micro-Electronics group, Tessera and Vern Solberg, Tessera consultant, may be contacted at [email protected]; www.tessera.com.

Read Vern Solberg’s series on flip chips for SMT.

Advanced Packaging, April 2010