MRS Day 2: CVD for Cu, low-k etch stop, future FETs, graphene “atom hopping”

by Michael A. Fury, Techcet Group

April 14, 2010 – The second day (Tues. 4/6) of the MRS Spring 2010 meeting in San Francisco ramped up to full throttle, with 38 symposia running in parallel. Highlights included CVD for Cu interconnects, controlling low-k etch-stop layers, inkjet-printed memory, materials challenges for future FETs, and "atom hopping" in graphene.

(See also: MRS Day 1 discussions, including charge-trapping NVM, organic electronics, graphene, and solar photovoltaics.)

(Underscored codes at the beginning of papers reviewed refer to the symposium, session and paper number; additional presentation details can be found in the MRS Spring 2010 program.)Click to Enlarge

F3.4. Yeung Au from Harvard described a selective chemical vapor deposition (CVD) Mn process for self-aligned adhesion and barrier layers in Cu interconnects. The Mn diffuses rapidly into the Cu, but after the capping layer is deposited, it diffuses back to the Cu surfaces due to the strong thermodynamic drive to form Mn nitride, oxide, or silicate. As a result, the Mn does not degrade the Cu conductivity. The dielectric surfaces can be passivated against Mn deposition, resulting in a selectivity of ~1100:1. The Mn also diffuses to the Cu sidewalls and trench bottoms, forming a ‘zero thickness’ diffusion barrier, thus allowing Cu interconnects without the requisite Ta/TaN or RuO2 barrier layer.

F3.5. Hung-En Tu of Taiwan’s National Chiao-Tung University explored the use of functional groups in porogen precursors to control the pore size and porosity in low-k SiCxNy etch-stop layers while maintaining the mechanical strength of the films. Polystyrene (PS) and epoxycyclohexane (ECH) were evaluated as sacrificial porogens. As PS concentration increased, both % porosity and pore size increased (from 18nm to 35nm). As ECH concentration increased, only % porosity increased; pore size was constant at 21nm.

G4.2. Tse Nga Ng from PARC showed a novel inkjet-printed NV FeFET memory device that uses silver electrodes and can retain 50% of output current over seven days. The experimental design allowed good separation of the various contributions to performance degradation, thus providing a good learning vehicle for further development.

J1.4. DARPA’s Todd Hylton discussed "Electronics for Intelligent Systems: Concepts and Devices." An intelligent system is defined as a universal computer capable of executing any input-output operation. A related concept, the thermodynamic state machine, responds to environmental input and evolves its internal algorithms to achieve a stable state relative to its environment. These behaviors can be exhibited by a TiO2/α-Si memristor device, which makes them suitable for casting in the role of synapses between transistors acting as neurons. The underlying objective is to build a machine that can evolve by its own actions, and not have all of its structure pre-embedded by the designers.

J1.5. Sayeef Salahuddin from UC Berkeley spoke on the possibility of negative capacitance in ferroelectric materials. Such behavior would significantly reduce the power dissipation in transistors. As a point of reference, the annual power consumption of all of the world’s Internet data centers is 150BkWh, and would rank between the national power consumptions of Mexico and Iran. The principle depends on the natural metastable state of the ferroelectric. While there is still no conclusive experimental evidence for -C, these effects are thought to be showing up in ferroelectric gate devices, starting with work presented at the 2008 IEDM.

J2.2. The grand materials challenge of reinventing the FET transistor was presented by Tom Theis of IBM Research. The convergence of device shrinks and fundamental limits puts us in the position of introducing new materials at the same time we are tinkering with the fundamental device physics. Historically, device scaling had been based on maintaining a constant field. Recently, we have switched to constant voltage scaling to ensure that we can turn the devices on and off. Some things to expect in our future include: CNT tunnel FET designs; a gate ferroelectric sandwiched between two paraelectric films; spin FET, though polarization needs to improve by several orders of magnitude.

J2.3. Tao He of the Beijing National Center for Nanoscience and Technology talked about controllable molecular modulation of conductivity in Si devices. As devices scale below 32nm, some structures may be controlled by as few as ten dopant atoms. Grafting molecular monolayers between the source and drain is one method for stabilizing conductivity. Such grafted layers can confer both gating and doping effects. These molecular effects have been seen to manifest through a 4.92μm thick Si layer.

J2.4. Sumit Chaudhary of Iowa State extended his group’s interest in OPV to develop a TiO2 ultrathin-film memristor by electrochemical anodization. Such devices are more commonly fabricated by ALD or sputtering. This work is expected to result in a workable design for a two-terminal memristive device.

J2.5. Robert Westervelt of Harvard CNS gave a prospective of graphene for future electronics. Electron movement in graphene is ballistic, with velocities of c/300 (where c is the speed of light). Devices can be contemplated in 2D (sheets), 1D (ribbons) or 0D (flakes). The flakes can hypothetically perform spintronic logic. A TEM beam can be used to cut graphene sheets for atomic-scale devices. The carbon atoms at the cut edge were observed in real time to hop around to find the lowest local energy state using a Zeiss Libra 200 TEM, which has a resolution of ~0.10nm — true atomic resolution. The video of atom hopping gets my vote for one of the coolest things presented all week.

J2.6. Jeremy Levy from the U. of Pittsburgh promised oxide nanoelectronics on demand, describing a method for producing extreme nanoscale electronic confinement at the interface between two normally insulating oxides, LaAlO3 and SrTiO3. A high-mobility electron gas forms at the interface. Using a conducting atomic-force-microscope probe, he can create nanoscale conducting islands, wires, tunnel junctions, diodes, transistors and photoreceivers with spatial dimensions comparable to the diameter of a single-wall carbon nanotube (~2nm). These structures are created in ambient conditions at room temperature, and can be erased and rewritten repeatedly.

Q1.1. John Rogers of the U. Illinois at Urbana has expanded from silicon to compound semiconductors for flexible, stretchable electronics. Using a simple wet etch undercut method, he fabricates triangular wires 0.5-1.0μm on a side out of semiconductor grade Si, GaAs, AlInGaP, and InP. Fully functional GaAs RF circuits were separated as a 200nm thick membrane from the bulk wafer and transferred to a plastic substrate, where they were integrated with stretchable interconnects. The resulting device continues to exhibit GHz response. This technology has been used to fabricate flexible sensor membranes that can be used in direct contact with a medical patient’s heart or brain tissue.

Q1.3. Lei Liao at UCLA fabricated nanoribbons and nanowires of high-k Al2O3 for use as the gate dielectric on top-gated graphene transistors. This high-mobility configuration gives a transconductance that is 10× higher than previous back-gated devices.

Q1.4. Michael Wang at Simon Fraser U. has developed a method for electric field-directed self-assembly of flexible semiconducting Se nanowires. The wires are precipitated from a solution of H2SeO3 and hydrazine, which is always fun in the lab. Rapid evaporation of the octanol solvent produces a non-woven fiber mat. Se is photoconductive, which lends itself to a variety of optical devices and switches.

Q1.5. David Taggart of UC Irvine characterized the electrical and structural properties of PEDOT nanowires produced by lithographically patterned electrodeposition. The conductivity of the resulting material is up to 4× better than thin-film PEDOT. In addition, the Seebeck coefficient of the nanowires is 2× better than bulk PEDOT for thermoelectric devices.


Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected]

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