MRS Day 4: TSVs and CMOS+MEMS, wafer bonding, CNT interfaces, ALD for rare-earth HK, graphene redux

by Michael A. Fury, Techcet GroupClick to Enlarge

April 16, 2010 – The fourth day (Thurs. 4/8) of the MRS Spring 2010 meeting in San Francisco was another full agenda of parallel sessions, although my reporting on the day is somewhat abbreviated. Highlights included: through-silicon vias (TSV) and flexible interconnects; 300mm BCB wafer bonding; carbon nanotube interfaces for interconnects and vias; phase-change memory devices; interfaces during atomic-layer deposition (ALD) of rare earth-based high-k dielectrics; and graphene as a key material for on-chip interconnects and transparent conductor electrodes.

(Underscored codes at the beginning of papers reviewed refer to the symposium, session and paper number; additional presentation details can be found in the MRS Spring 2010 program.)

F9.1. Muhannad Bakir at GA Tech showed a novel through-silicon via (TSV) approach for 3D CMOS and MEMS integration using mechanically flexible interconnects. The performance of many MEMS devices depends on mechanical stresses, which must not be perturbed by the packaging integration to CMOS devices. This work uses a mechanical flex interconnect (MFI) in place of solder balls to relieve the TCE mismatch stresses between the MEMS and CMOS devices. Fabrication uses a reflowable sacrificial polymer to form a dome, over which Cu is electroplated. After removing the polymer, the Cu structure provides a 20μm standoff with solder balls deposited on the tips. The new TSV process is designed to avoid CMP and any potential damage to the MEMS devices, and employs a perforated back-side oxide stop layer in which the etched holes are first plated over with Cu from the back side, filled with Ni from the front side, and then the via is filled with Cu from the front side. Finally, the oxide stop layer and Ni plugs are stripped from the back side.

Other MRS blog entries:
Day 3: Nanoimprint litho, 32nm memories, FET/Si/CNT sensors
Day 2: CVD for Cu, low-k etch stop, future FETs, graphene "atom hopping"
Day 1: Charge-trapping NVM, organics, graphene, PV

F9.6. Pratibha Singh of GlobalFoundries presented an optimized 300mm BCB wafer bonding process for 3D integration, capable of supporting 400°C Cu-Cu thermocompressive bonding. An important element of this process is a hard bake to crosslink the BCB prior to bonding, which is critical to avoid dendrite and void formation.

F10.3. Mark Strus at NIST described a reliability investigation of carbon nanotube (CNT) electrode contact interfaces for interconnect and via applications, using individual multiwalled carbon nanotubes (MWNT) welded to a Ni probe. For Cu contacts, both resistance and temperature rise as the voltage increases. For CNTs, the temperature decreases as the voltage increases, until just before a catastrophic failure. Details of the failure mechanisms are different for AC and DC testing modes.

F10.4. Bin Yu at Albany CNSE investigated some key reliability limits for on-chip interconnect applications of multilayer graphene systems. The mobility of graphene is 20× higher than Si and its thermal conductivity is 10× higher than Cu, making it an attractive design and fabrication material. The electronic structure is different for mono-layer, bi-layer, and tri-layer graphene; bi-layer graphene (BLG) was studied here due to its controllable band-gap tenability. BLG has a breakdown current density of 108A/cm2, 100× greater than Cu. The data suggests Joule heating as the primary breakdown mechanism.

G14.1. Ilya Karpov of Intel presented some characteristic behaviors, physical models, and key materials properties of Ge2Sb2Te5 (GST) phase-change memory devices. Device operation requires >1V gap between the set and reset threshold voltages, Vth, which are dependent on a critical field strength. This Vth is proportional to the thickness of an amorphous layer atop the GST device element. In the device configuration discussed, the amorphous-crystalline phase change is driven by the field strength, not by temperature. The physical limit for read speed is ~1ps, which is the lag time for the phase change after voltage switching, which occurs without diffusion.

I3.6. Luca Lamagna at Laboratorio MDM in Italy described the evolution of interface properties during atomic-layer deposition (ALD) of rare earth-based high-k dielectrics on Si, Ge, and III-V substrates. Runaway surface oxidation can be prevented during the early stages of deposition by use of process conditions that promote an interface passivation layer. Close study of the deposition mechanisms shows that the film thickness evolution can be separated from the growth rate evolution. The combination of substrate properties and ALD process parameters has a strong influence on the interface structure and subsequent film growth.

S10.1. Rodney Ruoff at UT Austin talked about his work on the science and applications of graphene-based materials. Free-standing sheets were fabricated by growing graphene on Cu foil (1000°C at 500 mTorr, 35 sccm CH4 in H2). The graphene is then coated with PMMA, the Cu is dissolved in acid, then the PMMA is dissolved in acetone. The graphene growth mechanism was explored in detail by alternating C12H4 and C13H4 in the inlet gas. Preliminary characterization results suggest that graphene may become competitive with ITO for transparent conductor electrodes.


Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected]

 

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