May 19, 2010 – Hashing out the complexity of both extending optical lithography and preparing multiple next-generation alternatives for high-volume manufacturing was the focus of a Confab talk (Tues. 5/18) by Naoya Hayashi, electronic device operations, Dai Nippon Printing Co.

Naoya Hayashi, DNP

Key messages from his presentation:

1) Beyond today’s ArF immersion (193nm) lithography, there are several next-generation lithography candidates jostling for position for likely use in various applications:

• Source-mask optimization: SoC 32nm, 22nm — extension of single-exposure method
• Double-patterning: spacer DPL for flash (3Xnm), pitch split for SoC?
• Maskless litho: development, small-volume for SoC
• Nanoimprint (NIL): HVM for memory. (More on this below)

…and they all require challenging mask technology. An EUV mask blank structure, for example, involves >85 layers (absorber to backside), eight different materials, and is 32nm defect free.

2) Extending optical may be desirable for logic devices, but it will require continued trickery (e.g., double exposure, double patterning, spacer double patterning). Source mask optimization (SMO), for example, can be described as a XYZ map of complexity:

• Source complexity, i.e. exposure latitude. Standard DOE, customized DOE (multiring, multipole), unconstrained DOE (diffraction order method, pixelated method);
• Mask complexity, i.e. constrained OPC. Rule-based SRAF, model-assisted SRAF/hybrid, Model-based SRAF, unconstrained/pixelated OPC; and
• Performance.

3) Of the NGL options, nanoimprint lithography (NIL) has particular appeal:

• Pattern transfer capability down to a few nanometers
• Simpler exposure tool and process (a "green technology"), with broadband UV light source, simpler optics, no resist coating/development processes; 75% less resist material reused than in a nominal process, and no developer exhaust; ~75% smaller tool footprint vs. EUV and ~50% of 193nm immersion; ~3% power consumption of EUV and same as 193nm immersion
• Less line-edge roughness and linewidth roughness degradation (direct transfer of the pattern from template, no acid spread function like chemically amplified resists)

NIL has captured 20nm defects, and possibly down to 1Xnm. The ITRS requires 2.3nm by 2013, and 10% CD change. Discussions are needed to hash out tool sensitivity, specs — and of course, cost. Collaborative efforts (e.g. Selete and SEMATECH programs) will be key. J.M.