In a system-in-package (SiP) chip stack, space constraints can lead to large parasitic inductances in the packaging. Planarity, processing, high-temperature exposure, and other factors also present challenges. A new anisotropic conductive adhesive technology could enable low-cost flexible packaging via a multi-layer particle structure. S. Manian Ramkumar, Ph.D., RIT, reviews the adhesives benefits to various levels of electronics interconnect.

The electronics industry is continuing its push for product miniaturization and RoHS compliance through innovative component technologies, PCB assembly technologies, and materials. For portable consumer products like flash, MP3 players and heterogeneously integrated RF systems, chip stacking using a system in package (SiP) approach is becoming more popular. In these space-constrained applications, conventional packaging techniques become very complex, and result in large parasitic inductances. Other challenges such as planarity, extra processing steps, and high temperatures arise while using a bumping and flip chip bonding approach. These challenges have renewed the industry’s interest in exploring the use of electrically conductive adhesives (ECAs) for various applications at the component packaging level and also at the lead-free PCB assembly level.

A novel anisotropic conductive adhesive (ACA) is currently available in the market to address these challenges and provide a means for low-temperature flexible packaging. Referred to as the ZTACH ACA by its manufacturer, the novel ACA uses a magnetic field during thermal or UV curing to align the particles as columns in the Z-axis direction (Figure 1). This method of aligning the particles as columns eliminates the need for pressure during assembly, to capture conductive particles between the mating surfaces. Unlike a conventional ACA, more than one particle is typically captured between the opposing surfaces with ZTACH. The formation of conductive columns eliminates bridging between adjacent pads, and has proven to accommodate varying lead configurations. Modification of the filler size and filler proportion enables control of the column density, column spacing, and the required contact pad area for minimum resistance. The novel ACA also enables mass curing of the adhesive, eliminating sequential component assembly. The ZTACH ACA offers numerous benefits for SiP assembly, including thin form factor, low assembly cost, and low parasitic impedances for high data rate, high-frequency applications. Unlike traditional ACAs, ZTACH ACA has a low parasitic capacitance because of the multilayer-particle structure after curing.

Figure 1.

The ZTACH material is being researched at the Center for Electronics Manufacturing and Assembly (CEMA) at the Rochester Institute of Technology (RIT) and at the IDEAS lab at Purdue University. The novel ACA’s applicability for PCB-level assembly has been successfully demonstrated by RIT. The research at RIT has also characterized the base material properties, analyzed the effect of various process parameters, identified failures, and investigated the ACA’s long-term reliability for surface mount PCB assembly. Specific characterization and analysis carried out by RIT include process parameters such as print thickness, placement speed, pressure and dwell, cure temperature and time, magnetic field strength, substrate finish, component termination finish, and leaded or bumped packages of varying configurations. Reliability testing included an investigation of the assembly performance in temperature and humidity aging, thermal aging, air-to-air thermal cycling, and drop testing conditions. The IDEAS lab at Purdue University has been using ZTACH to successfully implement highly integrated RF SiP modules using novel concepts such as reverse pyramid stacking and nested chip stacking. The Purdue research has also demonstrated that chip-to-chip silicon wafer interconnects assembled by manually dispensing ZTACH, without any additional preparation for individual chip I/O pad bonding, show very good RF performance, up to 90 GHz.
 
Thermal aging of the novel adhesive material has revealed improvement in contact resistance. Area array packages, with and without bumps, have shown variations in performance and have revealed the importance of placement pressure, speed, and dwell in achieving low initial contact resistance. Area array packages with bumps have provided consistent performance with low contact resistance. A mathematical model has been developed to model the column formation and prove its validity with experiments. The research published by RIT also indicates that immersion silver (ImAg), electroless nickel immersion gold (ENIG), hot air solder leveling (HASL), and organic solderability preservative (OSP) finishes outperform immersion tin (ImSn) finish during temperature/humidity aging. The research by the Purdue group has demonstrated successfully the use of ZTACH to package Tx silicon board for biomedical applications, such as the study of glaucoma in rabbits and mice. Note that glaucoma is predicted to affect about 60.5 million people by 2010. Biomedical implantable micro-systems, used in the study of medical conditions such as glaucoma, require exceptional levels of integration (300 × 300 × 300 µm3) and low profile (<50 µm), along with bio-compatibility. These features make ZTACH suitable for the 3D packaging required in these applications.

1. ZTACH is a trademark of SunRay Scientific, www.sunrayscientific.com

S. Manian Ramkumar, Ph.D., is an SMT Editorial Advisory Board member and professor and director at the Center for Electronics Manufacturing and Assembly (CEMA) at Rochester Institute of Technology (RIT). Contact him at [email protected]; http://smt.rit.edu. In the discussion of the novel ACA’s properties, Dr. Ramkumar fully discloses that he holds a small equity stake in SunRay Scientific. The material properties discussed here were derived from unbiased university testing at RIT under fully established compliance procedures and Purdue and not influenced by the company.

Advanced Packaging, June 2010, http://www.electroiq.com/index/packaging.html

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