by Michael A. Fury, Techcet Group

June 15, 2010 – Day 3 of IITC 2010 started with a second session on process integration. Kyung-Mun Byun of Samsung led off with a remarkable application of perhydro-polysilazane (PHPS, chemical formula [SiH₂NH] _n) SOG for gap fill in sub-30nm DRAM interconnects. Void defects and bit failures were both reduced substantially following optimizing the cure conditions to take advantage of the SOG viscosity minimum. Personally, I’m impressed that SOG is not only viable at 30nm, but it provides a unique solution to the gap fill challenges of this densely packed technology.

H.J. Yoo of Intel described an air gap interconnect demonstration on 32nm and 22nm single-layer test vehicles using 193nm dry lithography. The air gaps are applied to densely packed signal lines using non-critical lithography that is ≥2× the line pitch; gaps are not allowed adjacent to next-layer vias or large spaces. The low-k dielectric is removed from the designated gaps after etch patterning, so dielectric etch damage is not a factor. Note that with this process flow, the use of air gaps does not reduce low-k dielectric revenues at all. The resulting structures exhibited a 28% reduction in capacitance compared to non-gap structures. Further, there was no degradation in dielectric breakdown voltage, electromigration or thermo-mechanical reliability, and biased temperature stress results improved with the gaps. Evaluation on multi-level structures is now underway.

The session on novel materials and concepts began with a first step by Vincent Jousseaume of CEA-LETI-Minatec toward the growth of Si nanowires with a Cu catalyst at temperatures below 450°C, making it compatible with BEOL processing. Motonobu Sato of NEC then described a metal catalyst-free method for depositing PECVD multilayer graphene using a photoemission assist from the Ta retainer electrodes. The DC discharge plasma is activated by photoemission from the wafer surface as well as the Ta retainer electrode induced by UV irradiation from the 172nm Xe excimer source.

The second session on 3D and through-silicon vias (TSV) included Takayuki Ohba of the University of Tokyo showing a wafer-on-wafer (WOW) 3D scheme for 35nm SRAM and FRAM devices on both 200mm and 300mm wafers in which the top wafer is thinned to below 10μm before stacking and TSV fabrication. This wafer thinning does not degrade device performance, and the method appears to be ultimately extendable to stacked terabit devices based on 16Gb/cm² chip design — a stack of 60 or more chips in a 2mm package. Dorota Temple of RTI International presented a Cu/Sn-Cu eutectic system for 3D bonding at 210°C. The test vehicle had 325,632 connections at a 10μm pitch with an individual interconnect resistance ~100mΩ and 99.99% bond yield.

The final session on characterization and reliability opened with Kaz Hirakawa of the University of Tokyo examining electromigration in Au nano-junctions comprising several tens of individual atoms using a spectroscopic approach. Results indicate that the diffusion of atoms is driven by the transfer of kinetic energy from a single electron to a single metal atom, in contrast to the ‘wind of electrons’ model that operates in larger junctions. Masakazu Hamada from Panasonic gave the final paper of the IITC 2010 to an audience over 150 strong on a multilayer Ti/TaN copper barrier for 45nm porous ELK technology. The stack combination achieves good wettability with Cu at the same time it serves as a good Cu barrier, and realizes the benefits of both Ti and Ta simultaneously. For electromigration, Ti is 100× better than Ta, while for TDDB, Ta is 5× better than Ti. The stacked interface ELK/TaN/Ti/Cu appears to provide the best of both worlds.

On a final, more serious note: Silicon Valley authorities are considering whether or not they can make a case for enforcing Zafiropoulo’s Law in regard to fellow technology blogger Ed Korczynski, who was seen at the meeting sporting a ponytail without owning a Ferrari dealership.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].