Toshiba tips Si nanowires for 16nm chips

June 17, 2010 – Toshiba Corp. is revealing at this week’s VLSI Symposium in Hawaii a new silicon nanowire transistor for system LSI for 16nm node and beyond.

The device achieves a 1mA/μm on-current, a record for a Si nanowire transistor, thanks to reduced parasitic resistance and 75% better on-current levels, the company says.

As planar transistor architectures scale down in size, current leakage between the source and drain at off-stage ("off-leakage") is a critical problem; to answer this, transistors with 3D architectures are being investigated. Among these options are Si nanowires, which can suppress off-leakage and achieve further short-channel operation because their thin wire-shaped silicon channel is controlled by the surrounding gate — but parasitic resistance (especially under the gate sidewall) is still a problem.

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Figure 1: Structure of a silicon nanowire transistor. (Source: Toshiba)

To address this, Toshiba optimized gate fabrication and reduced the gate sidewall thickness from 30nm to 10nm. Epitaxial Si growth on the source/drain with such a thin gate sidewall improved on-current by 40% and realized low parasitic resistance. A further 25% increase in current performance was achieved by changing the direction of the Si nanowire channel from the <110> to <100> plane direction. The result: on-current level of 1mA/μm and off-current of 100nA/μm — a 75% increase in on-current, with no change in off-current condition.

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Figure 2: Comparison with the previous work. (Source: Toshiba)

Toshiba says it will continue to push development of this transistor, toward "establishing fundamental technologies for high-performance, low-power system LSIs." The work was partly supported by the New Energy and Industrial Technology Development Organization (NEDO).


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