SEMICON West Lesson #5: Interests outside CMOS

by James Montgomery, news editor

July 26, 2010 – The "Extreme Electronics" stage in the back corner of Moscone’s South Hall was packed all week long, offering discussions and presentations ranging from MEMS (see Pete’s writeup) to sensors to energy harvesting to flexible electronics. The talks we stood in on (no easy-access seats were available) were worth it.

MEMS had a big presence, both among exhibitors and the aforementioned presentation stage. Yole Développement sees a $6.5B MEMS device market in 2009 swelling to >$16B by 2015, and an even bigger surge in units: 3.2B in 2009, and 10B in 2015. iSuppli sees MEMS growing 11% this year to $6.B and expanding to $9.8B by 2014, a 10.7% CAGR; units will rise from 3.44B in 2009 to 4.14B in 2010, and 8.5B units by 2014 (a 19.5% CAGR). MEMS demand is so hot that even companies with internal MEMS fabs (e.g. Delphi, Conti) are exploring foundry sources, noted Yole’s Jean Christophe Eloy.

Better manufacturing technology for MEMS is pushing prices down, Eloy said. In 2000, accelerometers were 10mm2 in size, consumed 0.1mW, cost >$3.00, and were manufactured on 4-6in wafers. In 2010, devices are ~2-3mm2, made on 6-8in. wafers, consume 0.05mW, and cost $0.70. By 2020, MEMS devices will measure 1-2mm2, consume <0.05mW, cost <$0.4, and be manufactured mostly on 8-in. wafers (and will utilize 3D integration). "MEMS production is back on the fast track," said Jérémie Bouchaud, director and principal analyst for MEMS and sensors at iSuppli."

More "lessons learned" from SEMICON West 2010:
Lesson #1: Good times here, for now
Lesson #2: Capital intensity & EUV
Lesson #3: 3D and packaging are hot
Lesson #4: Supply chain challenges

Also fueling growth in MEMS is applications for consumer electronic devices and mobile handsets, which "bulldozed their way through the economic crisis," Bouchaud said. Inkjet printers will stay the dominant-selling MEMS device through 2014, ending the period with $2B/year.

High-brightness LEDs held the "Extreme Electronics" stage for every slot on Wednesday, reflecting that sector’s growing interest from semiconductor firms and suppliers seeking yet another new high-growth business. (HB-LED processing is something that suppliers will need to better understand, pointed out one industry watcher. E.g. wafers can sit up to half a day in a chamber vs. typical tool-to-tool flows for semiconductor manufacturing. And sapphire wafers are about to get much bigger — think 300mm.)

And of course everything Intersolar was right next door in the West Hall (exhibits) and Intercontinental (sessions), where traffic was even heavier (it barely thinned out as you went to the top of the three exhibit floors.) One question we heard, though, somewhat rhetorically: What happens if (when?) the solar side gets any bigger? How many solar panel demos can you fit in one expo center? We’ve heard Intersolar and SEMI remain committed to having a colocated show, so the question will be how to give Intersolar enough room to flex its muscles.

Semiconductors are everywhere

Bernie Meyerson’s Tuesday keynote identified high-level real-world applications where enabling technologies can make a fundamental difference in people’s lives, from managing urban traffic to pre-diagnosing sudden onset of diseases. At a SST-hosted breakfast on Wednesday (July 14), Andrew Thompson of Proteus Biomedical, developer of "intelligent" pharmaceutical devices that can be swallowed to monitor and relay body functions, preached for the marriage of information and technology and medicine. Among the planet’s 6-7B humans, there are roughly 5B cell phones in use — while only 3B people have shoes, he said. And the Internet reaches more people than water or electricity — it’s the world’s most important utility. (His grandmother witnessed the invention of everything from flight to refrigerators to TVs, he said, so surely we can come up with something.)

But it’s getting the message across to the masses (and influencers) outside our industry that’s the next big goal. We heard several times that the semiconductor industry (and tech in general) needs charismatic, intelligent advocacy to help Wall Street really understand the broad impact and potential of how what we do.

But eager ears are certainly out there — and maybe in surprising places. At our hotel this year, the concierge surprised us by revealing quite a bit more than a passing knowledge. Turns out he’s a U.Penn-pedigreed Ph.D — patented, with a handful of published papers — with a wide background in everything from narrow bandgap semiconductors to IR detectors and sensors to solar panels and nickel-hydride batteries. He’s still tracking what goes on in the industry, and has a keen interest to get back into the game after a hiatus. We’ve got his contact information if anyone’s interested.

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SEMICON West Lesson #3: 3D and packaging are hot

by James Montgomery, news editor

July 26, 2010 – There was a great deal of buzz at SEMICON West about 3D ICs, thanks to down-the-street ASMC presentations and backend discussions and vendors present. Through-silicon vias (TSVs) in particular are a hot ticket — so much so that traditional frontend equipment suppliers are touting their entry. (Novellus, for example, made a splash with a suite of tools for wafer-level packaging dubbed "The New Vertical Reality," staking claim to what it says is a $700M+ market.)

(Phil Garrou also summed up several 3D/TSV presentations from SEMICON West: the TechXspot session on "Bridging the Gap," and Suss Microtec’s "3D IC Bonding and Thinned Wafer Handling Workshop.")

There are more than 15 300mm 3D IC pilot lines now, according to SEMI’s Jonathan Davis, priming the Tuesday Executive Panel’s discussion about 3D ICs. Lam’s Steve Newberry predicted the industry will see widespread adoption in 4-5 years (maybe 2-3), though standards are needed to more efficiently implement it — e.g. will it be via-first, via-last, something else? It’s also a relatively small market (a "niche" for etch, in LRCX’s view), so ROI will be tough to justify for some, and few players will be able to pay for the R&D. AMAT’s Thakur takes a broader view of 3D IC opportunities, emphasizing formfactors and performance. GlobalFoundries’ Tom Sonderman likened TSV adoption to that projected for EUV lithography, requiring collaboration and a need to identify value-adds.

More "lessons learned" from SEMICON West 2010:
Lesson #1: Good times here, for now
Lesson #2: Capital intensity & EUV
Lesson #4: Supply chain challenges
Lesson #5: Interests outside CMOS

3D and TSV offer attractive growth, but there are still questions and hype to resolve. "While front-end semicap companies were very bullish on TSV, some back-end contacts wondered aloud how TSV will reach meaningful volumes soon as some critical standards are still not formulated," writes Credit Suisse’s Satya Kumar. Citing the challenge of getting market penetration with "more capable, but also more expensive tool sets, to an end market that has traditionally used low-end, very low-cost tools," Deutsche Bank’s Steve O’Rourke projects adoption of TSVs will start in traditional wafer fabs first, then "potentially" move to backend fabs, with prices lower — "but not by much" than traditional frontend tools. Winning strategies will present "a combination of capabilities and cost of ownership arguments," he writes — but "we maintain healthy skepticism on timing and market size expectations."

Though efficiency can offer a valuable proposition, it’s hard to overstate how hugely important are costs (low) and availability (now) to backend customers. Several people with whom we talked at SEMICON West about how traditionally more frontend-oriented tool suppliers are clamoring for growth in packaging suggested it might be a tough sell, especially at the subcon level. One industry watcher said that OSATs have a simple interface point for these folks: ask them about lead-times, and if the answer is anything more than three weeks the conversation’s abruptly over. Another pointed out that in many cases, backend outsourced firms translate "lead-time" as the time it takes to walk to the dock, unwrap the plastic from one of a long bank of tools already sitting around, and plug it in.

TI’s Cu pillars

Packaging wasn’t just a hot topic among suppliers. Texas Instruments made a splash with partner Amkor, announcing qualification and production of a fine-pitch Cu pillar flip-chip package — <50μm, vs. ~150μm pitch size limitations with conventional solder-based flip chip, e.g. ball bond.

Cu pillars offer advantages over conventional solder in terms of thermal performance, better conductivity, and resistance to electromigration, as well as shorter package routing (higher pin densities, reduced die sizes). The industry is investigating their use for various reasons, e.g. as an alternative to wafer-level packages for analog devices, or replacing gold wire in some packages. Intel uses Cu pillars in its 65nm and 45nm flip-chip products (and is expected to continue through 32nm).

TI executives explained the technology is ideal for applications ranging from ASSPs (smaller body size, high pin count, low-power aspects) to DSPs (same requirements), and power management (density more than pin count) — and they’ve got customers already lined up in all three product areas. "We looked at least two other alternatives" besides Cu pillars, and "we actually built products on them, they worked fine," noted Devan Iyer, TI’s manager of worldwide semiconductor packaging. "But on the long-term roadmap, we feel like Cu pillar is the most cost-effective, the most standard in the industry."

The TI/Amkor announcement "represents one of the major adoptions outside of Intel and I believe it is the start of the wave," Jan Vardaman, president/founder of TechSearch, told SST, in conversations during and after SEMICON West. She added that she sought out the first major product known to employ the Cu pillars, a hot-selling smartphone (whose backer rhymes with "Frugal") — but found it to be sold out in the wireless provider’s store, despite a stated retail price north of $600 (without a contract).

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