Pete Singer
Editor-in-Chief

The potential benefits of 3D integration — where chips are thinned, stacked and electrically connected with through-silicon vias (TSVs) – are by now well known for stacking memory and for communication chips. It provides an alternative to scaling when it comes to cramming more functionality in a smaller space. It could also enable an increase in performance by shortening signal paths. It could in theory also provide a pathway for improved yield, by portioning large die into smaller, higher-yielding blocks.

So where are we on the 3D integration quest? We’ve assembled a variety of inputs in this issue (and on our website) to address that question.

First, Sesh Ramaswami of Applied Materials describes process equipment readiness for TSVs. He says that unit processes are now ready and integration is well advances for typical process flows and that it’s "ready for limited pilot production at several locations." For full volume production though, he said wafer cost is still a concern, noting that the combined costs of wafer-level thinning (bonding, thinning and de-bonding) and die-level processing (dicing, stacking, assembly and test) are in excess of 50% of the overall cost. He said industry standardization could help reduce the cost of materials and accelerate the release of higher throughput equipment in this area.

Next, researchers from EV Group, Andong National University (Andong, Korea) and the Korea Institute of Machinery & Materials, report on work aimed at reducing the temperature of copper-to-copper bonding processes while maintaining strong bonding energies (still a problem area). By optimizing experimental parameters, the researchers achieved sufficient interfacial adhesion with no voids, even with a short bonding time of 30min.

Integration with TSVs, however, is not the only technology path to higher levels of integration in 3D. Navjot Chhabra of Freescale describes and alternative based on the redistributed chip package (RCP), first introduced in 2007. He notes that RCP technology provides for package size reduction, high yields, a cost-competitive process on a 300 mm tool set, and ultralow-k compatability among other advantages.

In a fourth feature, consultant Vern Solberg compares 3D integration to system-on-chip approaches (while also noting the many advances in traditional packaging technology). He says that developing custom silicon designs for SoC will take time and often require substantial resources but will eventually yield positive returns – at least for high-end or long-running apps. For other products having a relatively short life cycle, 3D die stacking or package stacking will have a decisive advantage in both time and economics.

On our website, an online feature authored by DEK’s Jeff Schake, Mark Whitmore, Dave Foggie and Michael Brown (Weymouth, Dorset, UK), describes how some of the more challenging process conditions now being encountered in volume production require die-attach coatings as thin as 38µm to be applied to wafers that have been mechanically thinned to as little as 150µm. With such thin wafers, and the requirement for low coating thickness, the wafer-support tooling surface metrology is expected to have an appreciable impact on coating thickness control. Thinner wafers may more easily translate deviations through their more flexible structure. The article discusses the flatness characteristics of currently available wafer pallets, and describes an experiment to measure and compare the process performance achieved when depositing an adhesive onto a total sample of 45 150µm thick, 200mm wafers, using six different types of pallets.

Also on the web, find an analysis of 3D activity at SEMICON West, penned by packaging expert and blogger Phil Garrou, and a variety of video interviews, including one with Sesha Varadarajan of Novellus. Varadarajan says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.

In short, as Chhabra notes, the hurdles to 3D integration begin with the design and modeling infrastructure and continue with the need for process and materials development. Costs need to be decreased through improved yields and standardization and, ultimately, ongoing reliability concerns must be alleviated as well. One industry source at SEMICON West bemoaned the fact that cost targets were set so early and then said to be met, when in reality the technology has yet to be fully proved in volume production. That might be the biggest challenge moving forward: resetting cost per wafer expectations.

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