(August 12, 2010) — The SMTA and Chip Scale Review magazine will host 6 half-day tutorials for the 7th Annual International Wafer-Level Packaging Conference. The IWLPC will be held October 11-14, 2010 at the Santa Clara Marriott Hotel in Santa Clara, CA. Tutorials will cover 3D packaging, future interconnects, WLP, flip chip, and more.
Early Bird conference pricing is in effect until September 10, 2010, after which registration prices will go up $100.
IWLPC tutorials are application-oriented and structured to combine field experience with scientific research to solve everyday problems. They are offered October 11 and 12.
Tutorial topics and presenters include:
- T1 – Three Dimensional Assembly, Packaging & Integration, Chuck Bauer, Ph.D., TechLead Corporation
- T2 – Advanced Packaging Technologies and Future Interconnection Trends, Joseph Fjelstad, Verdant Electronics, Inc.
- T3 – Wafer Level Packaging, Luu Nguyen, National Semiconductor Corporation
- T4 – 3D Packaging and WLP Evolution and Trends: Technology, Market, Supply Chain Infrastructure, Jean-Marc Yannou, Yole Développement
- T5 – Advanced Flip Chip Technology and Processing, Daniel F. Baldwin, Ph.D., Engent, Inc.
- T6 – Main Challenges and Key Technologies for 3D Integration, David Henry, CEA-LETI MINATEC
Sponsored jointly by the SMTA and Chip Scale Review magazine, the annual IWLPC explores cutting edge topics in wafer-level packaging and IC/MEMS/MOEMS packaging, including 3D/Stacked/CSP/SiP/SoP and mixed technology packages. The event is sponsored by Amkor Technology, EV Group, NEXX Systems, Pac Tech USA, and Technic Inc.
Visit http://www.iwlpc.com for more information or contact Melissa Serres at 952-920-7682 or [email protected] with questions.
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