(September 21, 2010) — REALITY, a European funded initiative on Design for Variability, has just finished its project mission. Over about 2.5 years, REALITY focused on developing industrially relevant innovative design techniques, methods, and flows for the design and analysis of energy-efficient self-adaptive System-on-Chips (SoCs). The tackled challenges include benchmarking the impact of the latest 32nm CMOS process manufacturing variability at all abstraction levels, from device to System-on-a-Chip level, while developing approaches to compensate their negative impact in the design of final products.

Full-scale 3D simulation of statistical variability associated with metal gate granularity and the corresponding metal work function variations have been carried out to clarify the magnitude of statistical variability in 32nm CMOS transistors with high-k/metal gate stack. For these devices the metal granularities can double the variability if the metal grain size becomes comparable to the transistor dimensions.

Also, a full statistical characterization of an ARM926 core has been achieved. A correlation between the timing, leakage and dynamic power has been demonstrated on local (within die) and non-local (above die) variations. The traditional corner analysis could be benchmarked with innovative statistical analysis techniques. Using the ARM core as driver, REALITY has confirmed that the SRAM components are responsible for more than the half of the variations on critical path timing. Hence, Statistical Timing Analysis (SSTA) flows that assume predictable timing response from these components may lead to over-optimistic conclusions. For that purpose REALITY has deployed a holistic statistical characterization flow including SRAM analysis.

With a novel flow integrating manufacturing variations and ageing effects for mixed-signal circuits, the REALITY project also developed a CAD environment that allows designers to make more accurate estimations and thus make circuits more energy and cost efficient.

Finally, REALITY evaluated the impact of process variation in SW-level metrics showing process variability is not only a concern for HW but for SW as well. Variability affecting multi-core multimedia platforms makes it hard to guarantee a certain QoS from the running application’s functionality. For that purpose, different circuit design techniques for system adaptation have been investigated, among them Adaptive Body Biasing (ABB). REALITY has shown that ABB can speed up a system-on-chip when, due to technology parameter variations, the manufactured product became too slow.

For further information on the REALITY project, contact Miguel Miranda, Project Coordinator, imec, Kapeldreef 75, 3001 Leuven, Belgium, [email protected].

The REALITY consortium involves 6 European institutions:

• ARM Holdings is a semiconductor intellectual property (IP) supplier, www.arm.com. Contact Person: Yves Laplanche, [email protected]
• Imec performs research in nanoelectronics, www.imec.be. Contact Person: Miguel Miranda, [email protected]
• STMicroelectronics supports multimedia convergence and power applications leveraging its array of technologies, design expertise and combination of intellectual property portfolio, strategic partnerships and manufacturing strength, www.st.com. Contact Person: Giuseppe Desoli, [email protected]
• The University of Bologna, founded in 1088, is the oldest academic institution of the Western world. It is one of most active Italian universities in research and technology transfer, and it is the top Italian University for 7th FP funding and project participation. Contact Person: Prof. Luca Benini, [email protected]
• Glasgow University is founded in 1451, the University of Glasgow is the fourth-oldest university in the English-speaking world. In 1840 the University became the first in the UK to appoint a Professor of Engineering, and in 1957, the first in Scotland to have an electronic computer. Contact Person: Prof. Asen Asenov, [email protected]
• K.U.Leuven, founded in 1425, is Belgium’s largest university. Contact Person: Prof. Georges Gielen, [email protected]

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