September 3, 2010 – Researchers at Rice U. say they’ve figured out that new switching memory they built with electrically manipulated 10nm graphite strips doesn’t actually need the graphite — good ol’ reliable silicon oxide will do just fine.

Last year a team led by Rice prof. James Tour showed that electrical current could break and reconnect graphite strips, creating a memory bit.

Now, grad student Jun Yao shows in a Nano Letters paper that the same thing can be achieved with silicon oxide between semiconducting sheets of polycrystalline silicon (as top/bottom electrodes); applying a charge forms a chain of nanosized silicon crystals — as small as 5nm — which can be repeatedly broken and reconnected by varying the voltage. As a proof of concept, he cut a carbon nanotube to localize the switching site, sliced out a thin piece of silicon oxide by focused ion beam, and identified a nanoscale silicon pathway under a transmission electron microscope.

What’s important here? Silicon oxide switches or memory locations require only two terminals, not three (flash memory) because the device doesn’t have to hold a charge. It also can be stacked in 3D arrays, which is the direction memory is going, and would be compatible with conventional CMOS manufacturing technology. And while there are questions about what to do with conventional memory below 20nm, "our technique is perfectly suited for sub-10nm circuits," Tour says in a statement. These SiO_x circuits offer similar specs as the original graphite device: high on-off ratios, "excellent" endurance, and <100ns switching. They’re also radiation-resistant (i.e. suitable for defense/aerospace radiation-hardened applications).

From the paper abstract:

Through cross-sectional transmission electron microscopy, we determine that the switching takes place through the voltage-driven formation and modification of silicon (Si) nanocrystals (NCs) embedded in the SiO_x matrix, with SiO_x itself also serving as the source of the formation of this Si pathway. The small sizes of the Si NCs (d ~ 5nm) suggest that scaling to ultrasmall domains could be feasible. Meanwhile, the switch also shows robust nonvolatile properties, high ON/OFF ratios (>10⁵), fast switching (sub-100ns), and good endurance (10⁴ write-erase cycles).

Austin design firm Privatran is bench-testing a silicon-oxide chip with 1000 memory elements, in work supported by a number of federal groups (NSF, plus the science arms of the Army, Air Force, and Navy). And a Rice spinoff company, NuPGA, is using vertical silicon oxide embedded in vias for rewritable gate array designs.