(October 14, 2010) — The 7th International Conference "3-D ARCHITECTURES FOR SEMICONDUCTOR INTEGRATION AND PACKAGING" will take place December 8-10, 2010 at the Hyatt Regency San Francisco Airport Hotel. Check out the planned keynotes and topics of the conference.
3D integration and packaging is now well known to all in the semiconductor industry. Today the focus has shifted away from trying to understand the technology opportunity to one of understanding the practical challenges of technology adoption and commercialization, including who is getting there first, how, and at what cost.
3D integration and packaging, of both devices as well as systems, represents an industry inflexion point, not just an evolutionary change — thus there is a natural degree of uncertainty as companies scramble to secure market share, obtain new process and design tools, and of course, new customers and new applications.
This conference continues to give a broad, yet thorough perspective on the technomarket opportunity and challenge offered by building devices and systems in the vertical dimension. Industry leaders from around the world are invited to speak at this conference, on a wide range of topics important to the emerging and ongoing 3-D integration and packaging efforts. The format of the conference and its presentations enables speakers to present the most up-to-date and forthright perspectives as possible. 3-D Architectures for Semiconductor Integration and Packaging targets senior-level technologists, managers, and executives as speakers and attendees from leading companies and organizations around the world. The result is a unique forum where one can gain the latest insights to bring clarity in the direction of their own efforts.
This year’s conference sessions include:
- Meeting the 3-D Opportunity
- Toward the Frontline of Manufacturing
- 3D Interposers — Where, When, and Why?
- Critical Perspectives on 3D IC Standards
- Facilitating Design of 3D Interposers and Die
- 3D IC Advancements and the Systems Approach
- Handling, Bonding, and TSV Manufacturing Capabilities
- New Routes to Logic
- Subramanian Lyer, IBM Fellow, IBM
- Douglas Chen-Hua Yu, Senior Director of Integrated Interconnect and Packaging Division, TSMC R&D Group
- Ho-Ming Tong, Chief R&D Officer & General Manager of Group R&D, ASE Group
- Antun Domic, Senior VP and General Manager Implementation Group, Synopsys
Pre-Conference Symposium: Key Topics in Going 3-D
The Evolving 3-D IC Infrastructure
Test in the Third Dimension
Thermal Management of 3D Architectures: Challenges and Opportunities
Taiwan R&D for 3-D ICs
Visit http://techventure.rti.org/Winter2010 for more details