by Laura Peters, contributing editor

October 18, 2010 – Researchers from the IBM Alliance have developed a new germanium ion implantation process that implants Ge into the shallow silicon channel region prior to high-k/metal gate (HKMG) stack depositions. The process allows superior low threshold voltage (V_t) modulation relative to aluminum or titanium caps for low-V_t pFETs. At the 16nm node, such an approach could eliminate an aluminum cap and solve the low-V_t problem. Ion implantation also overcomes the integration challenges associated with epitaxial SiGe channel formation, which requires hardmask integration and precise silicon recess and SiGe thickness control. The group that developed the process, from Toshiba America Electronic Components, IBM’s Semiconductor Research and Development Center, and STMicroelectronics in Albany, NY, will present their findings at International Electron Devices Meeting (IEDM) in San Francisco, CA (Dec. 6-8).

To achieve low-V_t modulation, the researchers compared aluminum to germanium channel ion implantation processes. The Ge implant was followed by a recrystallization anneal, interfacial layer formation, then HKMG deposition. undesirable hump in the C-V curve could be eliminated, the group determined, by using a cryogenic process in which wafer temperature was reduced during implantation. The Ge implant proved superior to the aluminum process because it lowered threshold voltage by as much as 500mV with no increase in equivalent oxide thickness (EOT, see figure below). Conversely, large degradations of EOT occurred with the aluminum ion implantation. Other electrical results were favorable including an improved gate leakage current density/EOT curve (J_g-EOT), low gate-induced drain leakage (GIDL) current, and slightly improved NBTI characteristics over the control.

Threshold voltage shift vs. EOT. The germanium channel ion implantation induced ~500 mV threshold voltage shift with no increase in inversion thickness. The aluminum ion implant provides large Vt shift but also large EOT degradation. (Source: IBM Alliance)

To better optimize the process, the researchers sought to determine the physical cause of the threshold voltage modulation. Backside SIMS revealed high Ge concentration near the gate stack/silicon interfaces, and the threshold voltage shift correlates well with the germanium peak concentration. Through a process of elimination and chemical analysis, they determined that pile-up of Ge atoms at the interfacial layer/channel interface determines the pFET threshold voltage shift. This physical cause of V_t modulation is completely different than that of a conventional epitaxial SiGe channel, where energy-band modulation is the key factor.