(October 25, 2010) — Over the years, undesirable process effects related to ion implantation have become well known; the like channeling effect, for example, and how to minimize it (screen oxide, fixed set point for twist-tilt angle and amorphous layer) for 25μm and 13μm mature technology. Patrick Demarest, Altis Semiconductor, describes how a stable process can emerge in data mining analysis for low final test yield, and provides definitions for incidence, tilt and twist angles, and channeling effects.

Why does a stable ion implant process on a 13μm CMOS product come up in the data mining analysis showing low final test yield? We have discovered that 13μm CMOS is sensitive to transistor leakage due to tilt and twist angle during triple well implantation. A fix was developed to avoid the channeling phenomena, drastically decrease leakage across the wafer, and increase final test yield.

The incidence angles at which accelerated atoms enter crystalline materials determine a large part of atom distribution. A misplacement of dopant distribution can greatly influence device performance. The total stopping cross-section of ions solids is divided into two parts: the energy transferred by the ion to the target electrons (electronic stopping), and the target nuclei (nuclear stopping) [1].

The angle between the normal wafer surface and the ion beam is the tilt angle. A zero tilt angle is used to avoid channeling effects in crystalline silicon, and introduce dopants. Additionally, the twist angle is necessary to describe completely the ion beam’s incidence direction. It is the angle between the plane containing the ion beam and the wafer normal, and the plane perpendicular to the primary flat of the wafer containing the wafer [4].The twist angle specifies the angle between the wafer notch, or flat, and the vector formed by the projection of the ion beam direction vector onto the wafer.

Channeling is an effect that results when injected dopant atoms travel along the silicon lattice and electronic braking determines their final position. The doping profile’s peak concentration is in a much deeper location than the amorphous or non-channeled mean projected range (R_p); in addition, the implanted dopant’s uniformity is degraded. There are two types of channeling: axial and planar. Channeling is reduced or prevented by several methods: proper tilting and twisting of the wafer prior to implant pre-homogenization of incident ions, or by implanting through a screen oxide and amorphizing the crystalline surface prior to dopant implantation via implantation of electrically inactive species such as germanium or silicon [2]. To prevent channeling effect in the first case, ion implant applications have employed a tilt angle offset much greater than the critical angle [3], and a twist angle that further misaligns incident dopant atom trajectory from the silicon lattice. The typical tilt/twist has been 7° tilt/22° twist.

Figure 1. FTY parameter spread on wafer with crescent phenomena.

Dispersion problem

Following CMP process improvement on the STI step for a specific 13μm product, we had a dispersion problem on the MinPower parameter in final test. Min-Power spread on the wafer is shown in Figure 1. It represents the product’s total leakage and was located in the wafers’ left portions with a crescent signature. Many investigations on different production steps were performed and the problem identified as the well implantation step.

The well implantation step is a triple-well CMOS followed by tailored implant for V_t (Table 2). This is a succession of three chain phosphorus implants, each in quad mode, to avoid shadowing problems, with a 7° tilt and 22° twist. A quad implant is done by dividing the desired dose into four equal portions, and then repositioning the wafer between each implantation segment. This allows the shadowing effects resulting from zero tilt to be symmetric around the device features giving the symmetric of the 0 implant without the associated axial channeling [5]. Table 1 shows standard recipe settings for segments of a standard quad implant (θ, Φ) – (θ, Φ+90) – (θ, Φ+180) – (θ, Φ+270). The quad implant Cartesian GSD parameters for 7° tilt and 22° twist are listed in Table 1, and the triple well implant sequence is 800kev in quad mode with total dose equal 1e14 at/cm² following by an implant 350Kev in quad mode with total dose equal 1E13 at/cm² and an im-plant 180Kev in quad mode with total dose equal 1E12 at/cm².

Figure 2. Phosphorus SIMS profile between left, center and right wafer with notch in the lower wafer.

Investigations and experiments

SIMS is an excellent technique for studying implant profiles that has superior elemental sensitivity. Improvements to the primary ion source have enabled SIMS to probe extremely shallow implants with superior depth resolution [6,7]. We did SIMS phosphorus profiles in the default region (left), in the center chip and in the right. The left chip phosphorus profile shows a big difference in profile tail and the deeper implant is the cause of the problem in Figure 2.

Figure 3. Sheet resistance mapping twist angle 27° with quad order modified as shown in Table 2.

We have run silicon wafers where ions are implanted into (100) Si N-types to ver-ify if the results match sheet resistance. We applied a triple-well implantation on the wafer, with the post implant anneal at 1060°C in a rapid thermal annealer for over 20 seconds. Sheet resistance mapping was done on a Prometrix using a four-point probe. The mapping displays the same figure in relationship with FTY mapping (Left mapping R_s in Figure 3). SIMS profiles on wafer sheet resistance veri-fied that the deeper implant was originated by a border channeling effect.

The segments could be implanted in the order shown in Table 2, where the segment with the highest beam angle rotation is done last, so that the crystal damage from earlier segment implants will minimize any differential channeling resulting from beam angle variations [5]. This allows the four-tilt and twist combination to be achieved with a minimum of across wafer beam angle variation [5].

Based on sheet resistance mapping, we have experiment some variations around tilt angle (22° to 27° tilt) and modify the quad segment order to see the improve-ment or the place of channeling area. In Figure 3, it can be seen that changing the twist angle from 22° to 27° decreases the channeling area on the left side of the wafer. We have verified by SIMS profiles that the deeper implant is now on the right side of the wafer.

Figure 4. Phosphorus SIMS profiles.

By changing the quad implant order, the area channeling is moved from the left to the right, dramatically reducing it. Figure 4 shows that by putting together the two process improvements with a 27° twist and changing the quad order, the channeling area is completely removed.

Figure 5. FTY min power parameters spread across wafer diameter — comparison between process twist 27° and process twist 22° (POR).

Results on product wafers and discussion

Experimentation was carried out on product wafers with implant angle settings 7° tilt and 27° twist and the quad order described in Table 2. When we compare MinPower parameter results in final wafer test (Fig. 5), a real improvement over the standard process of record is achieved. These recipe modifications (twist angles) show a considerable product improvement on the roll-off MinPower test.

Conclusion

We demonstrated that the tilt and twist angle on the well ion implantation near 800KeV for a specific 13µm product  is 7° tilt and 27° twist, with order quad implant optimization. Sub-0.1µm CMOS device will further impose other tilt and twist angle optimizations to account for NWELL resist shadowing and large depth variation caused by the high energy beam.

Acknowledgements
S. Leclerc and J.P. Cornier have performed the SIMS analysis. And thanks to my Altis Speed Team Members (F. Domart) for support and helpful discussions, and M. Bostelmann for support on Final Test analysis.

References
1. R. Simonton, A.F. Tash, “Channeling Effect in Ion Implantation into Silicon,” Ion Implantation Science and Technology, edited by J.F. Ziegler, 1996, p.214.
2. Ion Implant Applications Manual C.B. Yarling with W. Johnson, 1997 Ion Beam Press.
3. J.F. Ziegler, 1996, p.300 – 307.
4. Hoessiger, “Simulation of Ion Implantation for ULSI Technology,” PhD thesis in institute of microelectronics, Vienna, 2000, chapter 2.2.4.
5. Best methods and practice for minimizing beam angle variations on Axcelis ion Implanters, Axcelis Technologies, February 2003, part number 9511157
6. D. Lenoble, P. Prod’homme, D. Beutier ,C. Julien, Proc. of the 14th International Conf. on Ion Implantation Technology, Taos, New Mexico, USA, Sept. 22-27, 2002,(2002) 40.
7. S. Biswa, C.P.A. Mulcalzy, P.Banks, E.J.H. Collart, Proc. of the 14th International Conf. on Ion Implantation Technology, Taos, New Mexico, USA, Sept. 22-27, 2002, (2002) 244.

Patrick Demarest studied physics at the Rouen Institute of Technology, and semi-conductor physics at the Paris Institute, Arts et Metiers. He is an Ion implantation Expert process engineer with Altis Semiconductor, 224 bd John Kennedy 91105, Corbeil, France; ph.: 33 (0)1 60 90 92 12; [email protected]. 

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