by Michael A. Fury, Techcet Group

October 29, 2010 – The 7^th International Surface Cleaning and Preparation Workshop (Oct. 28-29 in Boston), organized by Northeastern and Hanyang universities, opened to an audience of about thirty researchers.

Jae Hyuck Choi of Samsung presented the current status and challenges of EUV lithography mask cleaning from an industrial perspective. Masks are fabricated using multilayered Mo/Si with a Ru cap. Cleaning processes include ozonated deionized water (denoted DIO₃), which can increase surface roughness, resulting in loss of reflectivity. Atomic H is capable of cleaning without degrading reflectivity, and is being incorporated in some systems immediately prior to mask use. Current processes are capable of cleaning to a 50nm & measuring to a 35nm particle spec, but the ITRS Roadmap calls for 23nm soon. Surface carbon contamination is a particularly insidious problem because it coats the features isotropically, including the sidewalls, thereby changing the mask CD.

On the topic of emerging materials in advanced devices, Mark Thirsk from Linx Consulting showed data on wafer starts vs. technology node, dramatizing how devices larger than 90nm still drive the huge volumes of wafer starts, but the device segmentation and advanced materials drivers take place below 90nm. High-dose implant strip & cleaning will drive UHP acid volumes, as the introduction of hard mask materials makes dry/wet strip processes less favorable than all-wet going forward. In contrast, STI PCMP cleaning of CeO₂ slurry calls for carefully controlled formulated chemistries. The process window for formulated Cu PCMP chemistry will continue to narrow as replacement barriers such as Ru begin to appear.

Takeshi Hattori, formerly of Sony and now affiliated with Hanyang U., talked about ultrapure water-related problems and their solutions in advanced semiconductor manufacturing. Silicon loss during wet cleans, device damage from megasonic energy, use of DI H₂O in immersion lithography, electrostatic charging during cleaning, and reduction of total chemical usage for environmental reasons are combining to drive a sharper focus on UHP water specs and dilute chemistry processes. Watermarks formed on wafer drying can be caused by formation of silicic acid in air; drying in N₂ can reduce or eliminate this. Marangoni drying with ultra-dry air (dew point -96°C) is replacing IPA in the latest DNS tools. When all else fails, Hattori-san showed a video using nano-chopsticks to physically pick up and remove nanometer-sized particles from a device surface.

Andreas Klipp of BASF talked about advanced Cu PCMP cleaning solutions for future technology nodes. They have refined a formalism for evaluating the effects of each functional additive individually and in tandem combinations with a combination of physical and electrical measurements. Their product pipeline includes an amine-free PCMP solution, "PlanapurAF 6," that operates at pH 6-7 with extremely low metal etching (1-2Å/min) and full recoverability of the k value on a porous k= 2.3 dielectric (Hg probe).

Rakesh Singh of Entegris gave an update on PCMP cleaning challenges and opportunities from the perspective of brush cleaning and related chemistries. PVA inherently has the negative zeta potential beneficial for particle removal; a new functionalized PVA makes it even more negative, thereby extending the effective pH range. Wafer-edge cleaning is improved by enlarging the PVA nodules at the ends of the roller. In an 18-month soak test in various dilute (1:60) commercial cleaning solutions, only an alkaline chemistry kept the brush clean and discoloration-free. It was inferred that this suggests more consistent cleaning performance in the short term. A wafer-sized PVA surface friction analyzer was co-developed with CETR.

Shohei Shima of Ebara showed measurements of surface potential non-uniformities using KFM (Kelvin) and EFM (electrostatic) techniques for analyzing localized defects during CMP. The two techniques are similar, but KFM includes a feedback loop for maintaining tip-surface separation. KFM scans correlated well with high Cu galvanic etch rates at the Cu/Ta damascene interface. EFM showed a variation of surface charge with pattern density and the differences in how it is influenced by Ar++ plasma, e-beam, and CO₂-water exposure.

A new damage-free nano gas cluster cleaning vacuum process for leading-edge surface preparation was presented by Hanyang U.’s Jin-Goo Park. Gas clusters (CO₂) are generated by jetting from high pressure into a vacuum through a supersonic (500m/s) nozzle; typical cluster size is 50nm at -60°C. Particle (25nm) removal efficiency was found to be >95% at gas flow rates of 10 liters/min. However, 60nm surface pattern damage throttles this back to 6LPM as the best compromise in this early work. As to the physical state of the CO₂ when it strikes the wafer, "we call it a cluster because we don’t know," he said.

Tae-Gon Kim from IMEC provided insights into chemical-mechanical cleaning and its future. These methods include megasonic and spray cleaning, both known to be capable of causing pattern damage. He used a mechanical nano-needle for direct measurement of the forces required to break a FinFET Si line, and characterized the differences between amorphous and poly-Si features. This data makes it possible to bracket the forces allowed in cleaning processes — high enough to remove particles, but not high enough to damage patterns. Megasonic bubble size is proportional to dissolved gas concentration. Larger bubbles exhibit stable formation and size oscillation over a fixed point on the wafer, likely leading to pattern and surface damage. Similarly, larger aerosol particles contribute to larger mechanical pattern distortion and damage. Damage risk notwithstanding, these chemical-mechanical methods will become more necessary as the intolerance to material loss from purely chemical cleaning continues to grow.

Shifting gears from semiconductors to solar cells, Ismail Kashkoush of Akrion Systems described the effect of pre-cleaning on texturing of crystalline Si wafers in KOH/IPA mixtures. This process involve high-throughput systems (3000-5000 wafers/hour) removing 5-10μm of Si. The KOH:IPA ratio is optimized to produce a narrow distribution of etch pyramid sizes, uniformly across the wafer, with the Si removal amount customized to maximize cell current efficiency. Inadequate preclean results in non-uniform texture, with contaminated areas exhibiting smaller pyramids and higher reflectivity. Good preclean results in a cell current efficiency gain of ~0.1% — but this is a significant benefit in terms of cell fab yield.

Bong-kyun Kang of Hanyang U. described the control of particle and carbon contaminants on Ru-capped EUV masks using dissolved gas DI water. Low material removal is the primary technical driver; low chemical usage is a primary environmental benefit. This study used dissolved H₂, O₃, or O₃ gas to modify the megasonic cavitation properties to affect better particle removal efficiency. At 2ppm, H₂ was more effective for megasonic particle removal than O₂in a dilute NH₄OH solution. DIO₃ was the most effective choice for removing carbon contamination from both the EUV mask substrate and the Ru capping layer, but results in an undesirable drop in reflectivity above 13ppm O₃.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].