(October 28, 2010) — Andrew Smith, Ventmark Technology Solutions, presents a 3D die stacking technology to address package miniaturization. Using bare die and vertical interconnect structures, this stacking technology permits the design of ultra-thin, near-chip-scale packaging (CSP) solutions without TSVs. Designers lacking custom integrated circuits (ICs) should look to new chip stacking technology to meet size and performance needs of integrating a range of devices into a small space.
Packaging technology’s evolution — from single-chip surface mount technology (SMT) packages to chip-on-board (COB) multi-chip modules and, most recently, package-on-package (POP) solutions — has greatly increased electronics density. Increasing demands for reduced size and increased functionality, however, often require higher levels of integration than current technologies support.
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Figure 1. a) Wire bond fan out from a multi-level stack; b) staggered die stack with spacers and wire bond; c) die stack with vertical interconnects and top side passive devices. |
With traditional stacked die structures, diminishing returns in real estate size are experienced as ever greater areas are consumed to accommodate the wire bond fan out from increased die count (Fig. 1a). Offset die and spacers (Fig. 1b) can also pose cost and complexity burdens.
The large upfront costs of developing a POP device make this technology most suitable for volume production applications, and leave other system designers with few options for downsizing.
3D integration with through-silicon via (TSV) technology offers the highest level of integration, but TSV is several years away from full commercial adoption. Currently, only CMOS image sensors are in volume TSV production, and integration of heterogeneous memory and microprocessors chips may not be available until 2014 [1]. Issues of cost reduction, thermal management, design and design for test must be overcome for complete TSV acceptance [2].
Bare die stacking using interposers and vertical interconnect structures (Fig. 1c) provides tight integration without TSV technology, or the upfront costs of a POP. Using traditional materials and processes in a non-traditional way, this approach leverages advances in wafer thinning, die bumping and flip-chip processes, in conjunction with high-density thick film ceramic to achieve a miniaturized system-in-package (SiP) solution at low cost.
Bare die stacking
As a flexible packaging technology, bare die stacking allows for the simple co-packaging of both identical and off-the-shelf heterogeneous die, as well as the incorporation of discrete and integrated passive devices. Applications include co-packing of microprocessors and memory (reduced size, improved performance), and custom memory stacks (greater memory/mm²). This die stacking concept also provides a highly scalable architecture, in X/Y and Z dimensions. As with other SiP approaches, functional design changes can be made at the SiP level without motherboard or other system-level redesigns, maintaining flexibility through the product life cycle. Creating a functional building block in a SiP device provides for device reuse across product lines, reducing front-end design effort in the product development cycle.
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Figure 2. a) Vertical interconnect structure; b) Ayre hybrid with vertical interconnects and top side passive devices. |
Vertical interconnect (VI) structures are a key element in the architecture of 3D die stacks, providing mechanical support within the stack and electrical connectivity between layers within the stack (Fig. 2). Using VI structures and eliminating wire bonds enables highly compact SiP devices in a variety of geometries created at low cost. These micro-miniature VI structures are interconnects fabricated from ceramic, and are fully customizable to the pin count and geometry required.
Because of increased power consumption/mm3, high thermal conductivity aluminum nitride materials provide additional benefits for the increased heat dissipation needed in SiP devices. VI structures can also be utilized to improve heat dissipation through the device with the addition of thermal vias, and offer an excellent temperature coefficient of expansion (TCE) match for improved reliability over a wide temperature range.
Vertical die stack case study
Vertical die stacking has application across a broad spectrum of system requirements, particularly where size and weight are at a premium, offering system designers a straightforward method to co-package critical elements of a design in a custom SiP to meet specific needs.
With materials inherently suited to high-temperature environments, vertical die stacking technology also provides a robust solution where size and ruggedness are critical, such as aero-engine instruments and down-well monitoring and logging. Typical applications include implantable medical devices, headsets, hand-held radios, wireless sensors, energy harvesting devices, body-worn devices, specialty memory product, harsh environment instruments, and hearing aids.
One such application is the Ayre Hybrid from On Semiconductor (Fig. 2). This micro hearing instrument packages a complete wireless audio system with DSP, near-field magnetic induction (NFMI) transceiver chip, memory and associated passive components into a device form factor of 1.85 × 36.8 × 6.48mm.
Packaging options
Vertical die stacks can be provided in a variety of formats to suit user needs. Finished parts can be epoxy-encapsulated, JEDEC-compatible SMT devices suiting standard pick-and-place assembly, or “raw” die stacks to be direct mounted into a hybrid package or COB assembly.
Multi-level die stacks are assembled in panel arrays before dicing into individual stacks. Building multi-level stacks in parallel minimizes lead times and provides opportunity for in-process testing at the sub-assembly level, improving first pass yield.
Conclusion
Vertical die stacking is a 3D technology available today, offering high integration without TSVs. System designers can benefit from the technology’s flexibility, size and weight, and integration. Vertical die stacking provides a simple means to co-package off-the-shelf die and passives devices in a mature production environment.
Acknowledgment
Ayre is a trademark of On Semiconductor.
References
1. Jan Vardaman, “3D TSV Markets: Infrastructure Requirements for Growth,” p. 13 RTI 3D Integration Conference Dec. 2009
2. Phil Garrou, Ph.D., “The 4 Horsemen of 3D IC, Perspectives from the Leading Edge,” Oct. 16, 2009
Andrew Smith studied mechanical engineering at Abertay U., Dundee, Scotland and is an independent contractor working in microelectronics packaging. He is currently the principal at Ventmark Technology Solutions, 211 Giant Oak Avenue, Thousand Oaks, CA 91320 USA; ph.: 805-795-3968; [email protected].
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