EUVL pattern distortions allow no holiday

(November 30, 2010) — At long last, there may be extreme ultraviolet light at the end of the next-generation lithography tunnel. Extreme ultraviolet lithography (EUVL) is a strong candidate for producing semiconductor chips at the 15nm node and below. EUVL introduces numerous new challenges to the entire IC manufacturing ecosystem, including the software used to correct pattern distortions introduced by exposure, resist, and etching processes. While the low k1 of EUVL would seem to provide a bit of an optical proximity correction (OPC) vendor’s holiday*, it’s shaping up to be quite the opposite situation. EUVL is introducing two major pattern-distorting effects at a magnitude never before seen: flare and mask shadowing. These effects combined create pattern distortions of several nanometers, and therefore cannot be ignored. Furthermore, the two effects vary in magnitude across the reticle in a complex yet predictable way. The implications of this are that the OPC software normally designed to simulate and correct for short-range (~1 to 2µm) pattern distortions will need to be adapted to these longer-range effects. In this article, James Word, Mentor Graphics, describes in detail these extreme UV lithography-specific pattern challenges and proposed solutions from the electronic design automation (EDA) software industry.

Optical lithography using 193nm illumination, combined with enhancements such as immersion, high-NA, polarized illumination, resolution enhancement technology (RET), and optical proximity correction (OPC), has provided the semiconductor industry with the ability to scale down to the 22nm technology node. It was not long ago that the industry was preparing itself for the end of optical lithography at the 65nm node, with the expectation that X-ray, E-beam, or some exotic (expensive and unavailable) technology would be required for further advancement. It is truly a tremendous achievement that this end-of-optical-lithography brick wall has been continuously pushed back. However, it seems that the end is near, and that below 22nm, the industry can only continue with existing optical lithography infrastructure by adopting costly, and maybe technically unfeasible, double-patterning. Below that lies a nightmarish scenario of triple, quadruple, and even quintuple-patterning. So it seems that EUV lithography, with its 13.5nm wavelength and many unsolved technology problems, may finally be the least-worst option for maintaining semiconductor technology scaling below 22nm.

EUV lithography patterning distortions

The remaining technical challenges for EUVL production usage include a need for higher source power, reticle defect inspection, improved resist quality and more. Correction of pattern distortions unique to EUVL is a particular challenge. There are essentially three sources of patterning distortions to be considered: proximity effects, flare, and mask shadowing.

Proximity effects. Proximity effects is a general industry term meaning pattern distortions that depend on the immediate environment of the feature in question. For example, isolated features often print larger or smaller than densely packed features. Proximity effects comprise contributions from optical, resist, and etch processes. Before considering proximity effects in EUVL, it is worth asking: Given that for the first time since the 0.25μm node we will be printing features greater than the illuminating wavelength, do we even need to correct for proximity effects? For a quick answer we can turn to the k1 factor in the lithographic resolution equation described in Table 1.

Table 1. k1 factors for several technology nodes. The numerical aperture (NA) values are based on expected maximum NA for state-of-the-art EUV scanners at the time of volume production.
k1 = W(NA)/λ
Technology node/Minimum width (W, nm)  Numerical aperture, NA  Wavelength, λ (nm)  Resulting k1 factor
250  .6 248  .60
130  .7 248  .37
22  .32 13.5 .52
15    .4 13.5 .44

Generally speaking, lithography becomes quite difficult, in terms of resolution and critical dimension (CD) control, below k1 = 0.5. The optical component of proximity effects generally increases as k1 decreases. However, the resist and etch components of proximity effects tend to increase as minimum width decreases. So, given the moderate k1 factor but very small minimum widths printed at 22nm and below, we can expect EUV proximity effects to be noticeable.

Still, as the simulated resist contours for 30nm lines shown in Figure 1 demonstrate, we will not be able to print EUV photoresist without somehow compensating for proximity effects such as line-end pullback, corner rounding, and proximity-dependent critical dimension errors. Further quantification of the level of EUV proximity effects can be found in references [4] and [6].

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Figure 1. 30nm lines simulated with calibrated optical and resist models within the Mentor Graphics Calibre OPCverify product.

Flare. The next challenge is the high level of scattered light in the EUV optical system, commonly referred to as flare. Flare is an incoherent light produced by scattering from imperfections in the optical system, and its presence can degrade image contrast and worsen CD control. Flare magnitude is primarily driven by the roughness of the mirror surfaces in the scanner, the wavelength (flare is proportional to the square of the wavelength), and local pattern density on the mask (clear, open, low-density regions suffer more from flare). Current optical scanners operating at 193nm wavelength suffer little from flare, but current EUV scanners have flare levels greater than 10% today, likely declining to around 5% in a few years.

One problem posed by flare is that the level of flare, and the impact on CD control, depends on local and global pattern density. Pattern density in modern integrated circuits (ICs), even when using dummy fill patterns, exhibits a large variation within a semiconductor chip. Previously published work shows that a 1% change in the level of flare within a chip will produce more than a 1nm change in printed resist dimension [1]. An example of how flare varies within a chip is shown in Figure 2.

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Figure 2. An integrated circuit poly layer simulated in Calibre, showing the variation in flare across the chip (blue = lowest flare, yellow = highest). Each color represents a 1% flare difference.

Mask shadowing. Mask shadowing is an imaging effect unique to EUV lithography. Due to the absorptive nature of optical materials at the 13.5nm EUV wavelength, EUV exposure tools can only use mirrors for all optical elements, as well as for the mask. Unlike the telecentric refractive projection lens systems used in optical lithography, EUV systems are non-telecentric at the mask plane — implying off-axis illumination of the mask. Currently, this angle of incidence is 6° from normal. In addition — and more problematic — is the additional complication of the azimuthal angle. This angle varies across the scanner’s illumination slit and ranges from 0° to ±22° [2].

Why is this off-axis mask illumination a problem? If the mask had no topography, and was infinitely thin, there would be no problem. However, the mask absorber does have a finite thickness, and the mask reflector is a distributed Bragg reflector composed of alternating thin-film layers. Thus, any off-axis mask illumination is going to result in an uneven shadowed reflection depending on the orientation of the mask shapes and the angle of incidence (Figure 3). The result of this mask shadowing effect is an orientation-dependent pattern bias and shift, which is also a function of the location within the scanner slit. Current estimates of the magnitude of this effect range from 1-2nm for longer lines [1], and >5nm for small 2D shapes like contact & via holes [3]. Variation in wafer CDs of this magnitude are unacceptable.

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Figure 3. Mask topography and azimuthal angles for left (a), center (b), and right (c) region of the scan slit. Detailed view (d) showing how the mask in the right region of the scan slit will shadow both incoming light from the source, and light reflected from the mask substrate.

EUVL pattern corrections by OPC software

Proximity effect compensation. Of the three primary sources of EUVL patterning distortions described above, proximity effects should be the most straightforward to handle within standard OPC software already in use by the semiconductor industry. The capability of off-the-shelf OPC software to correct for basic EUVL proximity effects has already been demonstrated [4]. What remains are the far more challenging flare and mask shadowing effects.

Flare effect compensation. Flare in microlithography and its impact on pattern distortions has been extensively studied in the past. There are already published techniques for measuring, modeling, and compensating for flare through software, mostly by rules-based OPC. In rules-based OPC, the flare levels are determined for each region of the chip, and a look-up table that associates flare levels to image errors is used to compensate the chip for the flare effect.

What is different now with flare in EUVL? The magnitude of flare will be significantly higher than it was in the days of optical lithography. That fact, combined with the sub-nanometer tolerance for allowed patterning error at the sub-22nm technology nodes, means that rules-based OPC methods are likely not accurate enough. The EDA industry is therefore being driven to develop model-based flare compensation functions that are built-in to OPC.

The biggest challenge in incorporating flare into OPC software is the very long range of the flare effect. The level of flare at any location within a chip is influenced by not only the immediate local environment, but by global pattern density levels many millimeters away. This long range of influence presents two challenges. The first is the long time to simulate the flare effect itself by traditional OPC models, which are designed for ranges of influence of roughly 1 to 3µm. This challenge has largely been overcome through the development of new simulation engines and models designed specifically to handle these long interaction distances. It is now possible to simulate an entire 26 × 33mm reticle layout with >15mm diameter flare models in about an hour. An example of the result of such a simulation can be seen in the previous Figure 2.

Once the flare map has been generated, and the local flare intensity within each 1µm grid point is known, we need to somehow utilize this information to mitigate the flare’s impact on printing. This can be accomplished within existing model-based OPC software with only minor enhancements to how the aerial image is computed. A simple formula where intensity is scaled by the total integrated scatter (TIS), and the local flare intensity is added to the image, should be an effective way of adding flare intensity to the OPC simulator. This method is currently being validated with actual wafer data.

Mask shadowing effect compensation. The physics underlying the mask shadow effects are reasonably well understood. In fact, TCAD lithography simulators can already accurately predict the effects. Unfortunately those models cannot be directly adapted for use in OPC due to their very long simulation times. Historically, the models used to describe the optical system behavior used by OPC software have been designed to be very, very fast as long as certain assumptions remain valid. These include an assumption of a thin mask with no topography (the Kirchhoff approximation), and an assumption of normal illumination incidence at the mask plane. Neither is valid in EUV exposure tools.

The effects introduced by mask topography alone are not necessarily unique to EUVL. Recently, mask topography has become a potential issue even with leading-edge optical lithography, as the thickness of the mask relative to the dimensions of the critical features being exposed and the wavelength becomes significant. This has led the EDA industry to introduce fast 3D mask topography models capable of simulating an entire chip with minor runtime penalty and with an accuracy approaching that of TCAD simulators. In addition, OPC models which correctly handle off-axis incidence at the mask plane are becoming available [5]. So it sounds like all the pieces are in place to accurately model the mask shadowing effects, right? Not quite. The one missing piece that requires further development is the ability to handle the fact that the angle of illumination incidence is now a function of the location within the scanner field (as shown in Figure 3). To overcome this limitation, the best solution now may be a hybrid of rules and model-based mask shadow compensation. Models to handle the field-location-invariant component, with rules to compensate for the field-dependent component, may provide sufficient accuracy to support the needs of R&D work for the foreseeable future.

Recent progress incorporating most of the above modeling, simulation, and correction technology for proximity, flare, and shadowing has demonstrated the ability of current and upcoming OPC software to handle the challenges posed by EUVL [6].


The upcoming availability of EUV scanners will provide the semiconductor industry with the ability to scale down to the 11nm technology node and beyond. Initially, the features being imaged by EUV scanners will be larger than the 13.5nm illumination wavelength, and this would seem to provide some breathing room to the over-worked OPC engineers of the world. But as we’ve demonstrated here, the unique illumination source, reflective optics, and reflective masks are conspiring to ensure continued full employment amongst these engineers. And as the industry shrinks down to 10nm and smaller minimum feature sizes, we can expect the challenges faced by OPC engineers to grow substantially.

*When 4× magnification steppers were first introduced in the 1980s, the size of mask features suddenly became 4× larger. This made mask manufacturing much easier, and thus initiated a brief period in the mask industry referred to as the "mask vendor’s holiday."

[1] G. Lorusso, G. Fenger, et. al., “Flare in EUV Lithography: Metrology, Out of Band Radiation, Fractal PSF and Flare Map Calibration,” J. Mico/Nanolith., Oct. 2009.
[2] A.M. Goethals, R. Jonckheere, et. al., “EUV lithography program at IMEC,” Proc. Of SPIE Vol. 6517, 2007.
[3] G. McIntyre et. al. “Modeling and Experiments of Non-Telecentric Thick Mask Effects for EUV Lithography,” Proc. Of SPIE Vol. 7171, 2010.
[4] H. Aoyama, Y Tanaka, et. al. “Applicability of extreme ultraviolet lithography to fabrication of hp-35nm interconnects,” Proc. Of SPIE Vol. 7636, 2010.
[5] K. Adam, M. Lam, “Hybrid Hopkins-Abbe Method for Modeling Oblique Angle Mask Effects in OPC,” Proc. Of SPIE Vol. 6924, 2008.
[6] G. Lorusso, E. Hendrix et. al., “Full Chip Correction of EUV Design,” Proc. Of SPIE Vol. 7636, 2010.

James Word is a product manager for OPC at Mentor Graphics. He has over 15 years of experience in the semiconductor industry in the areas of OPC and photolithography technology development. He has a BSEE from the University of New Mexico. Word can be reached at [email protected].


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