FDSOI-to-TSV-IEDM-preview-CEA-Leti research

(November 24, 2010)

IEDM Previews:
Intel fabs highest mobility pFET with Ge channel
University of Tokyo first to demo III-V self-aligned source/drain
IBM, Macronix identify phase-change memory failure mode
Record photodiode quantum efficiency from Taiwan lab
How strain can protect devices from ESD
SEMATECH tipping III-V MOSFET, FinFET, and resistive RAM
TSMC anneal for gate-last HKMG process
Imec IEDM presentations to cover More than Moore, ITRS
When do TSV stresses affect device operation?
Multi-threshold-voltage flexibility in FDSOI
CMOS imager works from light to night
Carbon nanotube vias approach production densities
IBM Alliance simplifies pFET HKMG
IM Flash details 25nm NAND

— CEA-Leti will present 10 papers, including two invited papers, at the IEDM/IEEE 2010 International Electron Devices Meeting December 6-8, in San Francisco, CA. The papers will cover More than Moore, FDSOI, memory (phase-change and charge-trapping), silicon nanowires, TSVs, high-k dielectrics, and more.

The two invited papers include an overview on FDSOI (the alternative to bulk technologies for 20nm nodes and below) and an overview of new-generation substrates enabling future devices in the More Moore and More Than Moore topics. A paper on the latest results in the integration of the metallic dual gate on FDSOI technology, with UTBOX, clearly positions Leti on the sub-16nm CMOS technologies. Leti will present two papers on memory, including one on the impact of N-doping in GeTe to boost the data-retention performances of phase-change memory (PCM), and an in-depth study on the role of defects in the Al2O3 blocking layer for charge-trapped memories.

Leti also will present findings of a futuristic study on the mobility of carriers in 10nm silicon nanowires for tomorrow’s CMOS (end of ITRS roadmap), and the latest results of its 3D through-silicon-via integration.

Two additional papers include results from Leti’s work on the reliability of oxide gate based on high-k dielectrics doped with Lanthanum, and CMOS ICs on SiGe on insulator and silicon constrain (co-integration into CMOS SRAM cell on FDSOI). 

CEA is a French research and technology public organization, with activities in four main areas: energy, information technologies, healthcare technologies and defence and security. Within CEA, the Laboratory for Electronics & Information Technology (CEA-Leti) works with companies to increase their competitiveness through technological innovation and transfers. CEA-Leti is focused on micro and nanotechnologies and their applications, from wireless devices and systems, to biology and healthcare or photonics. Nanoelectronics and microsystems (MEMS) are at the core of its activities. For more information about Leti, please visit www.leti.fr.  

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