IBM, Macronix identify phase-change memory failure mode: IEDM Preview

by Laura Peters, contributing editor

IEDM Previews:
Intel fabs highest mobility pFET with Ge channel
University of Tokyo first to demo III-V self-aligned source/drain
IBM, Macronix identify phase-change memory failure mode
Record photodiode quantum efficiency from Taiwan lab
How strain can protect devices from ESD
SEMATECH tipping III-V MOSFET, FinFET, and resistive RAM
TSMC anneal for gate-last HKMG process
Imec IEDM presentations to cover More than Moore, ITRS
When do TSV stresses affect device operation?
Multi-threshold-voltage flexibility in FDSOI
CMOS imager works from light to night
Carbon nanotube vias approach production densities
IBM Alliance simplifies pFET HKMG
IM Flash details 25nm NAND

November 19, 2010 – Phase-change memory (PCM) devices require high current density (5-20MA/cm2) to melt the phase-change material and change its state. During an investigation of the impact of current density and current polarity on cycling endurance, researchers from the IBM/Macronix PCRAM Joint Project discovered electromigration-induced failures when PCM cells are reverse-stressed. The team will report on this finding at the upcoming International Electron Devices Meeting (IEDM, 12/6-8 in San Francisco, CA).

Most PCM cell designs are asymmetrical, such as the mushroom cell design used in the IBM/Macronix cycling experiments. The structure consists of a TiN, cup-shaped bottom electrode contact (BEC) with interconnect, germanium-antimony-telluride (Ge2Sb2Te5 or GST) phase-change layer, TiN top electrode contact and copper back-end-of-line. Two cell connections (Figure 1), allowed either conventional bit-line-at-TEC (top electrode contact) cell operation or bit-line-at-BEC (bottom electrode contact) cell operation. By controlling the DC bias on the bit line and source line, current travels through the cell in either forward (TEC-to-BEC) or reverse (BEC-to-TEC) direction using positive pulses on the word line.

Cycling in forward-reset/forward-set mode, devices operated reasonably up to 108 cycles, while failures occurred in the reverse-reset/reverse-set testing after only 104 cycles. The impact of stressing at low current (40μA) also led to early failures when reverse-stressed cells became stuck open after 3 × 104 seconds. The high resistance of the stuck cells remained after several hours of baking at 165°C, indicating a failure similar to electromigration. The effect of varying pulse current (Figure 2) indicates endurance is more strongly affected by pulse current in the reverse-stressed cells.

Click to Enlarge
Figure 1: Two operating modes of the bit-line at top electrode contact (BL at TEC) forward array (top) and bit-line at bottom electrode contact (BL at BEC). With the bit line positively biased at VBL and VSL=0V, current through the phase-change element is controlled by the gate pulse.

TEM and EDX analysis of failed samples showed that for forward-stressed cells, there is significant depletion of Sb, Ge and Te, and Sb especially migrates toward the GST/BEC interface. In the reverse-stressed cells, Sb, Ge and Te depletion occurs, but located in a region on top of the bottom electrode contact. Since GST is a p-type semiconductor, in the reverse-stressed condition, holes flow from the BEC into the GST, causing potential voids.

The IBM/Macronix team suggests that PCM designs follow an asymmetric design and PCM operation should ensure current crowding only occurs in the direction of electron flow.

Click to Enlarge Click to Enlarge
Figure 2: In forward-stressing operation, endurance is reduced with higher pulse current, and the effect saturates when current is increased further (left). In reverse-stressed devices, endurance is much more susceptible to pulse current. High hole current may cause voids that cannot be repaired by the next melting (right).



Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.