ICPT 2010: Exceeding expectations

by Karey Holland, Techcet Group

November 29, 2010 – Overall, the >50 presentations and posters at this year’s International Conference on Planarization Technology (ICPT, Nov. 15-16 in Phoenix) exceeded my expectations for technical content. The presentations fit into general areas of front-end (STI, HKMG, and new device designs), back-end (Cu interconnect, barrier, etc.), emerging/non-traditional (quite an interesting mix), cleans and metrology, and modeling (including CMP mechanistic characterization). An electrochemist by training, I particularly appreciated the Porbaix diagrams and potentiometric polarization curves that were presented.Click to Enlarge

A series of presentations focused on the two CMP processes used in forming the high-k dielectric/metal electrode gate (HKMG) devices. Matt Prince of Intel led off Tuesday afternoon with a well-attended presentation about "Moore’s Law and Front-End CMP Challenges," in which he reviewed the roadmap that led to new CMP processes in fabricating the basic HKMG devices at 45nm. (This talk nicely complemented the keynote address from Intel 11X fab manager Ann Kelleher.) "Film thickness control and defects" were the "top concerns" during development, Prince stated, and they "will continue to be a challenge for new applications." (In support of this, an immediately preceding talk from Intel’s G. Kim focused on understanding/modeling within-die [WID] uniformity.) Prince hinted that new CMP technologies will be required after 32nm; what these are he left to our imaginations. The CMP aspects of HKMG process flow was shown with typical defect challenges. A key message (thanks to Intel’s Kelin Kuhn): Scaling drives down cost, but performance is now driven by materials rather than scaling. In summary, Prince stated some needs which elicited additional (nervous?) laughter from the audience:

  • R&D needs materials suppliers to deliver new slurries and pads, with tunable properties, in days not weeks;
  • Slurry development must continue to evaluate multiple pad types, and vice-versa;
  • More development is required on post CMP cleaning (i.e., chemistry & brushes);
  • Equipment needs to deliver tighter film thickness control, while improving end-point and metrology capabilities.

A valuable reminder: the last big push for new interconnect materials, e.g., Cu and low-k, lead to careers made or broken, and businesses made and broken.

K. DeVriendt from IMEC and T. Du from Fujimi presented specific polish process papers on the poly open dielectric CMP and Al replacement metal gate planarization, respectively. While HKMG is today only a small segment of the CMP application market, this will grow as more devices make the transition from SiO2 and silicide gates to HKMG. DeVriendt and Ong (also from IMEC) presented two new front-end processes, which may be used for technologies beyond 22nm and after HKMG devices: vertical Si nanowire tunnel FET (CMP is used to open the top of the Si nanowires) and "Ge for high mobility channels." F. LeQuéré (CEA-Leti) presented a paper on mesoporous silicon structures. H.J. Kim (Samsung) presented papers on microscratch characterization and reduction, observing that not all microscratches result in chip failure. And Intel’s Prince, reinforcing one of his key concerns, commented that while some defect may not be a killer defect in this generation, they may be in the next generation, and he could not accept any microscratches for this reason.

IBM presenters focused on interconnect technology. Papa Rao explained that low-k materials have higher dielectric constants after CMP that can be modulated by pad and slurry choice. Independent of what causes an increase in dielectric constant, either a plasma or UV treatment appeared to release the contaminants from the dielectric’s matrix and allow them to volatilize. He postulated that the plasma treatment improvement was likely caused by the UV emissions that heal the low-k film. Don Canaperi (IBM) discussed a well-balanced process optimization with low solids slurry for barrier removal. The process required a balancing act that optimized electrical yield (shorts/opens), defects (including metal residuals), remaining topography, and wiring resistivity (copper erosion).

Other CMP copper interconnect process papers were presented by X. Gu (Tohoku University), J. Koh (Hynix), L. Lu (Epoch/Cabot Micro), A. Kiesel (GlobalFoundries), S. Kondo (Renesas), and A. Natarajan (IBM), collectively doing a good job focusing on development for reducing copper erosion, CMP effects on low-k, and all defects. K. Okutani (CASMAT) discussed pattern density effects and how connecting high-density lines to large pads can effect on Cu corrosion. A few presentations focused more on the consumables interactions with each other and the interconnect process. These included new particles (F. Nemouchi, CEA-Leti with ST and BASF), scaling challenges and novel methods of passivating materials from CMP attack (L. Cook, Dow), post-CMP rinse caused Cu surface microroughness (T. Hirano, Fujimi), and the effect of pad and slurry on interlayer dielectric (ILD) polish (S. Li, Cabot Micro).

On the CMP characterization front, university and fab people are doing some intriguing work. There were several papers that used various techniques to study pad asperities, their height, contact area, and implications for scratching defects, and the presentations involved discussions of some very interesting metrology techniques. These include T. Eusner (MIT in conjunction with Intel), R. Duyos Mateo (Tohoku University + ASU), K. Kimura (Kyushu Institute of Tech), J. Chien (Berkeley), S. Bott (Fraunhofer), S. Jung (Gwangju Institute of Science & Technology), and A. Reddy (Dow). An interesting study of zeta potential on the pad materials, presented by P. Sides (Carnegie Mellon University with Intel), should continue our understanding of pad surfaces and their interaction with particles, slurry chemistry, and cleaning. C. Cheng (Dow with KLA-Tencor) discussed methods of measuring haze as a CMP defect. X. Liao (University of Arizona with Entegris) showed that slurry bow wave thickness can be changed by carrier ring design. Models to help us understand how consumables interact were presented by G.S. Kim (Intel) and J Yang (Samsung).

The general area of emerging/non-traditional CMP applications included several on GST (Ge2SbTe5) and through-silicon vias (TSV). M. Suzuki (Asahi Glass) presented a ceria slurry process optimized for polishing the wafers’ backs to open the bottom of the deep copper TSVs. An interesting proposal to purposefully dish Cu TSV for improved alignment was presented by H. Jeong (Pusan National University). J-Y. Cho (Hangyang University with Hynix) discussed corrosion mechanisms for GST post CMP with and without H2O2 slurries.

Additional CMP applications included PRAM damascene structures. V. Balan (CEA-Leti with ST) and T. Pfau (Entrepix) presented CMP process information on packaging applications for Medtronic. H. Cui (Hangyang University) found that when polishing SiO2-Ta, polyacrylamide has a strong affinity for Ta and adsorption reduces the Ta rate, with no affect on the SiO2 rate.

It is hard to beat the environment of Phoenix in November, and even better was to have a meeting in this environment that continues to move the industry forward in process learning, characterization and improved understanding of CMP processes.

Karey Holland, Ph.D., managing partner at Techcet Group, has >25 years of experience in semiconductor technology, including CMP equipment company SpeedFam-IPEC, IBM (where she contributed to interconnect technology development and manufacturing introduction of IBM’s 4Mb DRAM), SEMATECH’s deep-UV lithography Micrascan II project, and Motorola’s microprocessor and memory technology group. Contact: [email protected].


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