(November 17, 2010 – Marketwire) — Verific Design Automation and Veridae Systems jointly announced that the Verific front-end software has been licensed to Veridae for inclusion in the new Clarus family of debug and validation products.

Verific’s Verilog analyzer and static elaborator is a platform for parsing the IEEE Verilog standard, allowing Clarus to work with a comprehensive internal representation of a register transfer level (RTL) design rather than the original Verilog language. Verific’s tools are tightly integrated with the Clarus family, technology based upon research activity at the University of British Columbia (UBC).

The Clarus family of products provides visibility into complex systems on chip (SoCs), field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) at all stages of validation, allowing engineers to quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly move devices into production. Debug problems that previously required weeks, or even months, can be resolved in hours.

Veridae chose Verific based on its reputation in the electronic design automation (EDA) and semiconductor community as the supplier of de facto standard front-end software for hardware description language (HDL) design. In addition to supplying the front-end software, Verific’s founder and president Rob Dekker provided support on the best technical approaches to interfacing the Verific software with the Clarus tools.

Veridae Systems Inc. provides debug and validation technology that enables engineers to bring complex ICs from prototype to production. Learn more at http://www.veridae.com/

Verific Design Automation provides front-end software supporting SystemVerilog, Verilog and VHDL design. Learn more at www.verific.com.

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