(December 16, 2010) — Raj Jammy, VP, materials & emerging technologies at SEMATECH, explains the details behind the work done on paper #26.3 (“Contact resistance reduction to FinFET source/drain using dielectric dipole mitigated Schottky barrier height tuning”) during IEDM 2010 (12/6-12/8/10, San Francisco, CA). The research group demonstrated contact resistance reduction using dielectric dipole-mitigated Schottky barrier height (SBH) tuning on a FinFET source/drain (Figure 1). Reduction of the SBH by 100meV from the AlO_x/SiO₂ dipole results in a 10Ω-µm² reduction in specific contact resistivity and a 100Ω-µm reduction in FinFET source/drain resistance (R_S/D) (Figure 2).

Single metal S/D contact to simplify integration   Achieved using dielectric mitigated dipole SBH tuning (DDM-SBH Tuning)   Utilizes intrinsic high-κ/SiO2 interfacial dipole
Figure 1. Overview of research for IEDM 2010 paper #26.3. SOURCE: SEMATECH

It is necessary to reduce the access resistance to devices — if it is high, there will be performance losses. The researchers consider contact formation without the need for silicide to be very promising for emerging devices, alternative channel materials, and sub-22nm CMOSFETs. Jammy details the theory behind the research in this interview and, later in the podcast, he provides further notes on the trend to implant-lite technologies for doping and how industry will be able to bring different doping technologies together down the road.

Listen to Jammy speak at IEDM: Download (for iPhone/iPod users) or Play Now

"As we continue to scale different technologies, one of the problems is the resistance that comes into the accessing of the specific device," Jammy tells Debra Vogler, senior technical editor, ElectroIQ. "You might be applying strain engineering, high-mobility channels, or other approaches to boost performance — but if the access resistance to the device is very high, you lose quite a bit of that performance." The group focused on mitigating that problem using the fact that it has been known for some time that the barrier height between the silicon and the contact silicide becomes a significant portion of the performance loss as devices get smaller. "You can adjust the barrier height by implanting specific species, or you can co-implant different species along with the nickel silicide."

Figure 2. Contact resistance summary. SOURCE: SEMATECH

The approach SEMATECH pursued was dipole-assisted Schottky barrier tuning. The group borrowed some ideas from high-k and metal gate (HKMG) stack engineering in which dipoles are intentionally introduced to modulate the work function, which is not very different from trying to modulate the Schottky barrier height for the work being done in paper #26.3, according to Jammy. "By using SBH tuning, one achieves a better conduction mechanism through the junction, which helps us continue scaling without necessarily losing any performance."

More from IEDM 2010:

• Which transistor path? FinFET, tri-gate, FDSOI, Ge/III-V, bulk CMOS…
• III-V MOSFET on 200mm Si fabbed using industry-standard tools
• 2Xnm NAND, 3D integration, graphene FETs, biosensors
• Dopant solutions target cost-effective semiconductor miniaturization

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