IEDM 2010: Inside Renesas’ eDRAM structure

by Debra Vogler, senior technical editor

December 17, 2010 – At the IEDM 2010 conference (San Francisco, 12/6-12/8), at Renesas Electronics Corp. presented a paper (#33.3, "A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics,") in which it announced a new structure of logic IP-compatible (LIC) eDRAM for the next-generation system LSIs at the 28nm node and beyond. In a briefing at IEDM, Yoshihiro Hayashi, senior chief engineer at Renesas’ LSI Research Laboratory, told SST about the details of its research.

Unlike stand-alone DRAM memory, it is very important that eDRAM be compatible with standard CMOS logic IP, which is integrated in an eDRAM chip, Hayashi explained. "Our new eDRAM technology embeds the capacitors, the data storage elements in DRAM, in the interconnect layer used for the logic circuits," he said (Fig. 1). "This makes it possible to create embedded memory that seamlessly combines the globally standardized logic circuit IP." The key concept of the development, he noted, here is a scalable logic IP compatible (LIC) eDRAM (Fig. 2).

Figure 1: Advantages of eDRAM.


Figure 2: eDRAM devices compatible with standard CMOS-logic IPs (logic IP compatible [LIC] eDRAM).

By embedding the cylindrical capacitors in the interconnect layer instead of forming a layer independent of the interconnect layer, this new technology obviates the need for the long bypass contacts that were formed between the logic area transistors and the interconnect layer. "The parasitic capacitance and parasitic resistance due to the bypass contacts is reduced, thus preventing degradation of logic circuit performance," Hayashi told SST. "As a result, it is now possible to design eDRAM at the 28nm node and beyond using IP developed for use in standard 28nm node CMOS logic." He explained that the idea of placing a cylinder capacitor into the interconnect layer itself was very simple in eliminating the long bypass contact. Because standard logic IP in 28nm node CMOS uses a porous low-k film in the interconnect layers, it was necessary to prepare a cylinder capacitor with the dielectric constant k=2.5 in the porous film.

The researchers had to overcome two challenges: 1) the cylinder in the porous low-k film had to have a steep profile to keep the capacitance large, and 2) the metal electrode for the capacitor had to be deposited directly on the porous film using chemical vapor deposition (CVD) (Fig. 3).

Figure 3: Illustration of technical challenges in LIC-eDRAM.

To tackle the first challenge, the team developed a special lateral etching process to adjust to a tapered profile (Fig. 4). "It worked well, and we were able to achieve almost a 90° steep profile of the cylinder," said Hayashi.

Figure 4: Fabrication of a steep profile cylinder.

With a conventional thermal CVD process, the gas-phase metal precursor molecules penetrate into the porous film comprised of large open pores just like a gas filter, explained Hayashi. To overcome it, the team controlled the pore size on a molecular scale, and developed a special porous film with 0.4nm diameter pores. "We call this film the ‘molecular pore stack’ (MPS) film, where the molecular size of water (H2O) is 0.6nm, but the pore size is much smaller." By introducing this MPS film, the metal contamination in the porous film was "profoundly suppressed" because it was much smaller in diameter than that of the conventional porous film, which had a pore diameter of more than 1.0nm (Fig. 5).

Figure 5: Control of the pore structure.

According to Hayashi, however, these solutions were not sufficient to address the challenges that faced the researchers. "When applying the conventional thermal CVD method, the metal atoms, such as Ni, were only 0.2nm in size, which is smaller than the pore size in the MPS film," he said. "This allowed a few metal atoms to penetrate into the MPS film, so we needed additional technology to achieve zero contamination metal."

By this point in the work, the team realized that it had been focusing on the metal deposition process — not the conventional thermal CVD, but the surface-absorption type CVD method. Namely, the metal precursor molecules, such as organic titanium, are designed to be larger than the pore size of MPS, and are absorbed on the MPS surface. The molecules absorbed on the surface then react with NH3 gas to form conductive metal-nitride, TiN on the MPS surface (Fig. 6). "We have successfully confirmed that no metal had penetrated inside the MPS film," Hayashi told SST. "Therefore, we finally decided to utilize the molecular-level control technology for both the porous low-k film and the metal film.

Figure 6: Blocking of metal diffusion by surface-absorption-type TiN CVD on MPS.

Adopting the unique MPS film for the interconnect layer has suppressed the diffusion of metal electrode material into the porous low-k film attached to the capacitor sidewalls, according to Hayashi. The team reported that it was able to assure a lifetime of over 10 years for the porous low-k film between 50nm-spaced capacitors required for eDRAM at the 28nm node. "There is no apparent difference in both the electrical properties and the dielectric reliability that was observed between the new cylinder capacitor buried in the interconnect layer and the conventional one in SiO2, under the interconnect layer (Fig. 7)," Hayashi said.

Figure 7: Plots showing cumulative probability vs. capacitance,
leakage current, and TDDB of the cylinder MIM capacitor.



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