IEDM Reflections, Day 2: SRO for 11nm multigate CMOS, memory updates

by Michael A. Fury, Techcet Group

December 16, 2010 – The second morning of IEDM 2010 (Tues. 12/07) continued the frenetic pace of the first afternoon, though the seven parallel tracks are still much easier to navigate than the 30-50 concurrent sessions of an ECS or MRS meeting. The difference here is that all of the tracks are highly relevant to the semiconductor world.

(Additional information can be found online at 2010 IEDM Technical Program. All figures are reproduced with permission of IEDM.)

14.1: My morning started with an invited talk by S.G. Wuu of TSMC describing a 0.9μm pixel CMOS image sensor with backside illumination. This is a work in progress, as spatial resolution is good but color fidelity is still inferior to the analogous 1.1μm device. Critical process elements include high-precision wafer thinning uniformity, and short-pulse laser-melt annealing of the backside + shallow implant. Pixel scaling was achieved with tighter litho design rules and a 4× reduction in PR non-uniformity, to improve pixel isolation. New ARC materials and microlens structures were implemented to accommodate a pixel size approaching the wavelength of visible light.

Schematic of BSI process flow.

11.2: To a standing room only crowd of over 300, S. Monfray of STMicroelectronics introduced a planar multi-gate CMOS design with a 4nm Si conduction channel for the 11nm node, with the offer that this self-aligned gate concept may be the gateway (pun not intended, but I’ll keep it) to the continuation of CMOS scaling for a while longer. The scheme can be implemented as either gate first or gate last. Self-alignment is achieved with selective etching of the SiGe/Si/SiGe stack. HSQ and e-beam are used for patterning the double gate.

Top: Process steps to integrate the self-aligned planar multigates. The gate stack material can be the final gate stack (gate-first approach) or a sacrificial one (poly-SiO2) for a gate-last approach.
Bottom: Perfectly self-aligned gates after the trench filling (left) and the SiOx removal (right). The HSQ approach opens an innovative way for an easy self-alignment of planar multigate devices.

11.3: The saturation drain current ID,Sat of AlGaN/GaN MOS-HEMTs was enhanced by 30% with a transconductance improvement of 22% by using a highly compressive (~6GPa) DLC liner, according to X. Liu of the National University of Singapore. The compressive stress of the DLC liner effectively counteracts the tensile stress of the AlGaN layer. Introducing the DLC layer also reduced VT by ~1V.

Schematic view of a AlBaN/HaN MOS-HEMT with a compressive diamond-like carbon (DLC) liner. The density of two-dimensional electron gas (2-DEG) decreases with application of compressive stress.

12.4: Another SRO crowd of 300+ packed in to hear S. Hong of Hynix talk about trends for current and future memory technology. Only five companies remain in the high-volume memory business, leaving four sources of DRAM and four sources of NAND flash (three of the companies do both), he pointed out. Also, both DRAM and NAND flash are at risk for scaling below 20nm unless new technology elements can be successfully implemented. One candidate for DRAM capacitors is a complex TiN/ZrO2/Al2O3/ZrO2/TiN stack for an EOT <0.5nm with less leakage than high-k alone. Air gaps may provide a partial solution for floating gate NAND. Samsung, Toshiba, and Hynix all have projects on the table for 3D NAND. PCM is currently the most developed advanced memory, but only addresses the NOR flash market. STT-RAM, he suggests, is the only candidate for replacing DRAM for high speed and endurance; its non-volatility is a great bonus. ReRAM is a viable candidate for storage applications, but is still all over the map in terms of materials, cost, and performance.

13.5: For a change of pace, I checked out the Power Devices session to hear M. Kanechika of Toyota Central R&D talk about SiC and GaN power electronics for automotive systems. For 2nd-generation hybrid vehicles, startup will continue to rely on motor only, while cruising will balance between motor and engine as required. Both braking and engine operation will be used to regenerate battery charge. SiC vertical devices are being improved by using higher-quality SiC substrates fabricated with a process of repeated A-face crystal growth. This has been demonstrated in the lab but is not yet ready for prime time. GaN up to now has been used for lateral devices, but is being driven to vertical structures for higher power applications (10kW vs. 1kW planar). Performance characteristics demand a mix for each hybrid vehicle: vertical devices for DC/AC inverter and DC/DC boost converter; and lateral devices for DC/DC buck converter and AC/DC charger.

Motor power and power source voltage for the current released HEVs and EVs.

11.6: Gate leakage can be reduced >10× in ALD HfZrO high-k gate stacks by replacing RTP annealing with room-temperature UV/O3 annealing, but only if you deposit the dielectric in multiple deposition steps with multiple anneals. L. Wu of Nanyang Tech reported that this multi-step approach also increases the dielectric breakdown strength by 0.3V and TDDB life time by 10×. The benefits are believed to be due to grain boundary suppression through the healing of oxygen vacancies, as indicated by STM & XPS studies.

Top: TEM pictures confirm that all samples annealed at different condition have similar EOT, ~1.3nm IL and ~2.0nm HK. (a) RTP 600°C 30s; (b) UVO 2nmX2; and (c) UVO 1minX4. Clear crystallization is observed in RTP samples.
Bottom: Schematic showing how MDMA (UVO annealing) can potentially improve HK film quality: (1) with UV light, oxygen can be cooperated into the HK film to heal the Vo, especially along grain boundaries. (2) with multi-deposition, the grain boundaries, which can serve as leakage path inside the film, could be disconnected due to the healing of Vo, thus leads to leakage reduction.

14.7: In a late news paper, S. Jeon of Samsung’s SAIT proposed a novel transparent photosensor array with triple oxide TFTs as both switches and sensor elements. The design is motivated by large area interactive touch screen displays. The dielectric stack is a-HfInZnO/InZnO/HfInZnO at thicknesses of 250Å-1000Å-750Å respectively. IZO has a very high photosensitivity, while that of HIZO is negligible. The bottom HIZO serves to adjust VTh to positive, while the top HIZO functions as a passivation and etch stop layer. The use of HIZO layers also compensates for the intrinsically slow response time of IZO, enabling frame rates >150Hz. The sensor pixels are integrated between the display pixels.

Left: Circuit diagram of a unit pixel for a proposed sensor utilizing 2-transistor structures having fully transparent oxide semiconductor.
Right: Bottom-gated sensor and switch TFTs utilizing various active stacks, and a single-amorphous HIZO layer, respectively.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected]


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