by Michael A. Fury, Techcet Group

December 22, 2010 – The third day of IEDM 2010 (12/08/10) began with seven parallel sessions as did Day 2. The only unique session that was not a continuation from the previous days was on characterization, reliability and yield for RTN (random telegraph noise) in memory devices. I, however, found other topics of greater interest personally.

(Additional information can be found online at 2010 IEDM Technical Program. All figures are reproduced with permission of IEDM.)

27.1: A new FinFET process for 22/20nm devices was presented by C.C. Wu of TSMC, made possible largely by a litho/etch integration scheme that produces very vertical fin sidewalls. The resulting structure give comparable I_On /I_Off for both PFET and NFET devices, and claims a best-in-class drive current. The data showed a 100× reduction in leakage current compared to comparably sized planar devices, and the HKMG reliability is similar to planar devices as well. A manufacturable 0.1μm² SRAM cell was shown.

Left: Top view image of the high-performance 0.1μm2 SRAM bit cell showing good pattern fidelity. Right: IOn /IOff curves show IOn = 1200 μA/μm for NFET and 1100 μA/μm for PFET at IOff =100nA/μm at VDD=1V.

29.2: PCRAM for embedded memory applications was raised from a vertical to a planar device using a phase-change (PC) dog-bone structure between two electrodes, as shown by K. Attenborough of the NXP-TSMC Research Center. Devices were successfully embedded in a 65nm CMOS process using doped Sb₂Te. Proper encapsulation of the PC layer is critical to device performance and reliability. The PC layer requires three additional masks, and is completed before standard Cu BEOL begins. The operational switching range is between 10³Ω and 10⁶Ω states. With an optimized PC material, device lifetime is projected to be 10 years at 95°C.

31.3: Autonomous microelectronics systems are, by definition, required to provide their own power sources. One way to achieve this is to build a solar cell on top of the CMOS circuitry, which is what J. Lu of the MESA+ Institute for Nanotechnology talked about. Both amorphous silicon (a-Si) and copper-indium-gallium-selenide (CIGS) cells were integrated with 0.25μm Al BEOL and 0.13μm Cu BEOL. Compatibility issues of adhesion, mobile ion contamination, plasma induced damage, peak process temperatures and mechanical stress were all noted and addressed successfully. CIGS is best integrated on the chip backside, while the wider process window for a-Si makes front side integration preferred. It was never clear to me in the Terminator stories if this is how Skynet got started.

Top: , comprising a PV cell for energy collection; power management circuits in CMOS; integrated energy storage (high-density capacitor or solid-state battery) and low-power circuits. The PV cell can be realized on the chip’s front (CMOS) side or the back side. Bottom: Schematic cross-section of a-Si solar cell on CMOS chip (left) and CIGS solar cell on CMOS chip (not to scale).

32.4: Returning to the graphene session, K. Majumdar of the Indian Institute of Science simulated a dual gated device with doped semiconductor source & drain and a bilayer graphene (BLG) channel. The bandgap-free nature of graphene is overcome by inducing a bandgap with the dual gates. Objective of the modeling is to obtain complementary unipolar BLG FETs for logic devices. The simulated device characteristics compare well with state of the art Si technology, with I_On /I_Off >10⁴ and a subthreshold slope of ~110mV/decade for a 20nm gate length.

(a) Schematic of a d with source (S) and drain (D). (b) Bandstructure of an unbiased infinite BLG film with zero bandgap. (c) Bandgap opening in a "Mexican hat" shape under applied external vertical field. (d) Typical experimental transfer characteristics of a metal S/D BLG FET with on-off ratio of ~100 at Vdd=1mV and T=295K.

27.5: In the quest for superlatives, N. Butt of IBM SRDC laid claim to the smallest embedded DRAM cell (0.0394μm2) and the densest memory integrated into the highest performance 32nm HKMG SOI logic technology with 1.5nsec access time at V_DD of 1V, and up to 13 levels of Cu interconnect. This deep trench eDRAM reportedly outperforms SRAM for cache-hungry multi-core processors, with 3-4× smaller area, 5× lower standby power, and 1000× better soft error reliability. ‘Nuff said; I’m impressed.

DT resistance extracted from S-parameter measurements for different trench processes. Inset shows the TEM image of HK/DT node stack.

31.6: At first it wasn’t clear to me why you would want a device that can switch its energy harvesting from PV to TE (thermoelectric) modes, but I have seen the light and felt the heat. T. Suzuki at Fujitsu Laboratories demonstrated an organic thin film device that can do both. When the P/N stacks are connected in series, you have a PV device; in parallel, the same stacks function as a TE device. One of the key process tricks is to dope the first P3HT layer with an atomized solution of FeCl₃ and anneal it at 150°C for a uniform doping profile. Target applications include wearable healthcare monitors.

Schematic cross-sectional view of a hybrid device. A mixed layer of PCBM and undoped P3HT, which consists of a so-called bulk hetero-junction PV cell, is formed upon a doped P3HT. TE power is generated in doped P3HT film. The chemical structures are also shown.

Typical application using the hybrid PV/TE module. The hybrid device on a flexible substrate would be highly effective as a wearable healthcare device in the conditions where light irradiation is not essential. (a) Test module fabricated on a flexible substrate. (b) Schematic cross section of the flexible hybrid module. Copper films were patterned alternately on an upper and lower film. The difference in the thermal conductivities of copper and PI films yields the thermal difference in a P3HT film, and generates electric power in TE mode. (c) Cross-sectional view of a typical flexible module.

29.7: Replacing hard drives with NVRAM is now a bit (no pun intended) closer to reality in S.J. Whang’s paper from Hynix R&D 3D dual control gate NAND flash with a surrounding floating gate (FG). This DC-SF NAND is fabricated as a vertical device through an alternating stack of poly and oxide layers. The control gates prevent charge spreading in the floating gate, resulting in reliable retention characteristics, and also provide shielding so that FG-FG interference is low at 12mV/V. Stacking the multi-bit (2-4 bits/cell) DC-SF NAND provides a path to file storage devices of 1Tb and beyond.

Cross-sectional schematic of DC-SF NAND flash with sharing FG structure implemented in this experiment. Bird’s view of DC-SF NAND flash. Surrounding FG has capacitive.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail [email protected].