(December 14, 2010) — Among the papers SEMATECH presented at IEDM 2010 (12/6-12/8/10, San Francisco, CA) was #6.2 ("Self-aligned MOSFETs hetero-integrated on a 200mm Si substrate using an industry standard process flow"). According to the group, this was the first demonstration of self-aligned III-V MOSFETs hetero-integrated on a 200mm substrate and fabricated with state-of-the-art industry standard silicon processing tools. The researchers demonstrated devices with Lg=500nm, Ion=471µA/µm at 1V Vcc gm,ext=1005µs/µm. 

Figure 1. III-V on silicon: from modules to VLSI. SOURCE: SEMATECH

Raj Jammy, SEMATECH VP, materials & emerging technologies, describes in detail the challenges that had to be overcome to complete the MOFET research, in this podcast interview with Debra Vogler, senior technical editor, ElectroIQ.

Listen to Jammy speak at IEDM 2010: Download (For iPod/iPhone users) or Play Now

This work is significant because most III-V transistor studies have been done on smaller substrates (e.g., 4″ or less). "We are trying to make III-V MOSFETs as we would on 300mm and probably on 450mm in the future, using industry-standard tools," says Jammy. "These tools help us to make really fine geometry devices as well as some very advanced transistors." III-V semiconductors are interesting because they have high mobilities, much higher than silicon. The ability to lower power dissipation is also attractive, allowing operation at much lower voltages. "We want to move this research from the lab stage to the fab stage."

Figure 2. MOSFET mobility is not limited by heterointegration. SOURCE: SEMATECH

Challenges the researchers had to overcome include: 

  •  getting the right quality of epi layers of III-V materials on top of silicon. You need a thick buffer layer, but that is not necessarily a guarantee; 
  •  forming junctions in III-V materials is different from silicon because of the danger of destroying the lattice structure. You have to be very cautious in annealing and the dopants are very different;  most III-V materials use gold, platinum, or palladium contacts, which are contaminating in a conventional silicon fab. The SEMATECH group used nickel and germanium-based contact materials;
  •  and the selection of materials for high-k and metal gates had to be researched as well.

Jammy also commented on the move to implant-lite, or implant-free gate stack engineering — a trend that will gain importance going forward because of the desire to limit damage to the substrate (which causes leakage) from the implant process itself. The SEMATECH group looked at how to mitigate the damage from conventional implant and then also evaluated non-traditional approaches, where ultra-thin layers of a dopant material could be deposited and driven in, something akin to the diffusion process used in the past, but in a more sophisticated way. "We ended up with something in the range of 2-5nm deep, but very active — the dopant is highly activated and the sheet resistance is very low," said Jammy. "Since we are moving to 3D devices, for example, memory technologies are on the cusp of moving to 3D — how do you implant into such structures…so we have to come up with new methods."

Also read:
Analyzing noise in modern MOSFETs
III-V MOSFETs: beyond silicon technology

More IEDM in-depth discussions:
Which transistor path? FinFET, tri-gate, FDSOI, Ge/III-V, bulk CMOS…
Dopant solutions target cost-effective semiconductor miniaturization: SRC and Waseda U. at IEDM 

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