Each year, we ask a variety of industry executives for their viewpoints on what they consider to be the main technical challenges in the year head. You’ll find their complete responses on our website, www.electroiq.com, but here’s a compilation of some of their comments.
Andy Antonelli, Director of External Research & Development, Novellus Systems, Inc., sees a range of challenges at the 22nm node, transistor structure liners with step coverage better that what can be achieved with conventional PECVD, and ALD is not an option. When it comes to interconnects, copper will not replace tungsten as the contact metal, but a substantial shift in the deposition process is needed to lower the resistance. "A multi-step deposition process including a pre-treatment, nucleation layer, and bulk fill, perhaps at different temperatures, can be shown to substantially increase the grain size and thus decrease the resistance of the contact," Antonelli said.
David Hemker, VP, New Product Development, Lam Research Corp., sees "no obvious disruptive changes" with the 22nm generation, he said the ongoing evolution of device technology involves increasingly complex multi-layered structures. "As the number of layers continues to grow, device architectures are becoming more sensitive to the interactions of film interfaces. This dynamic is beginning to have significant influence on process integration," he said.
Weimin Li, Deposition Director, Advanced Technology Development, ATMI, Inc., agrees that while 22nm still has a number of challenges, many of the changes are evolutionary, not revolutionary. Moving beyond 22nm, however, is the start of the revolution as DRAM makers face replacing ZrO2-based dielectrics. "After decades of research on SrTiO3-based (STO) dielectrics, is it finally time to make it reality?" Li asks. Delivering the right ratio of Sr-to-Ti throughout a3 -D capacitor structure with extreme aspect ratios – across hundreds of billions of structures per wafer and millions of wafers per year – is a significant challenge.
Nick Pugliano, Marketing Director, Advanced Pattering Technologies, Dow Electronic Materials, sees major challenges at the 22nm node in the area of lithography. "The industry is keenly aware that a single-exposure solution such as EUV will not be ready for 22nm due to its own set of challenges," he said. "Thus, the 22nm node has emerged as a proving ground for a variety of innovative patterning processes geared toward on-track, low cost-of-ownership technologies." For example, quadruple-patterning is needed, but a simple multiplication of double-patterning would be costly and extremely difficult to deploy in mass production.
Franklin Kalk, CTO, Toppan Photomasks Inc., adds that, for mask manufacturers, the conditions and challenges at the 22nm (32nm half-pitch) technology node are becoming clear. "Immersion argon fluoride (ArF-i) will remain the preferred critical-layer lithography. Double patterning (DP) and source-mask optimization (SMO) methods will both become pervasive for image features at sub-80nm pitch. While extreme UV (EUV) lithography is not yet production-ready, several pre-production EUV scanner deliveries are scheduled for 2011, with production tools following within two years. We expect a concerted effort to employ EUV for memory production at 32nm half-pitch, even if only in a limited fashion," he said.
Arthur W. Zafiropoulo, Chairman & CEO, Ultratech, Inc., sees many challenges surrounding the materials selection for 22nm. "As we see the 20/22nm structures begin to be implemented, there will be a larger percentage of those wafers packaged by using (flip-chip) bump. There is an increase in demand for bump in a larger percentage of wafers, as the industry shifts from wire bonding to bump packaging, he said. "
Doug Dixon, Marketing Communications Director, Henkel, says environmental concerns are not the only thing keeping packaging specialists awake at night. "Without question, the smaller, thinner, more powerful paradigm is here to stay and is challenging traditional design and assembly rules, ultimately putting greater demands on the materials needed to enable their function. Much thinner wafers (≤50µm) and the ability to stack die to unprecedented heights (32 die stacks) has driven die attach materials innovation to address these new requirements," he said.
A common theme among our respondents: tackling 22nm technical challenges will require closer collaboration between IC manufacturers and their suppliers. See www.electroiq.com for the full comments from these and many others, and see page 20 of this issue for a roundup of what analysts are saying about the business outlook for 2011.