Analyst’s take: Why the gate first-last debate isn’t over

by James Montgomery, news editor

January 24, 2010 – At the Common Platform Technology Forum (Jan. 18 in Santa Clara, CA), execs declared that they will switch from a gate-first approach to a gate-last approach starting with the 20nm process technology node, essentially reversing their position stated for years now. Analysts told SST why the CPA had a change of heart, why it’s not unexpected, and why other concerns will very soon overshadow this switchover.

There’s been a schism about gate structure at the ≤32nm node: a camp of gate-first proponents, led by IBM and CPA partners, and a gate-last approach being implemented by Intel as well as TSMC (and UMC has a hybrid approach). Each side claims benefits and ways to deal with drawbacks. "Gate first is simpler and lower cost as the conventional flow, but Vt tuning and thermal budget are critical," summed Gartner foundry analyst Sam Wang. "Gate last can use spacer for stress tuning and mobility enhancement, but has more complex process and design rules." Gate-first has an edge with low-power dissipation devices; gate-last is more ideal for high-performance ones.

Chipworks’ Dick James has a great technical explanation of the gate first-vs.-last history and why gate-last is (for now) the winner. But what else can we take away from this?

— It wasn’t needed at 28nm… According to the IBM-led CPA, gate-first was a better choice at 28nm for a number of reasons: scalability relative to 40nm, enjoying less restrictive 40nm layout style advantages, faster speed and reduced energy/switch, and a smaller die vs. a gate-last approach. Vt tuning range (>>300mV) can be done with process knobs, and it offers repeatable low- and superlow-threshold voltage options.

Gate-last proponent TSMC, meanwhile, offers a number of gate-last arguments of its own: speed, power, reliability, manufacturability, and scalability. Device power consumption can be minimized with process knobs, it says, and threshold voltage is kept stable via thermal processes done before HKMG deposition.

…But it’s inevitable at 20nm. While the jump from 40nm to 28nm was seen as perhaps easier using a gate-first approach, "the arguments regarding leakage and performance probably couldn’t be ignored at 20nm," said Gartner research VP Dean Freeman. Added James: "My take is that the gate-first guys underestimated the difficulties of making a stable process […and] it’s turned out to be a real pain." Gate-last is a more complex process flow — there is added mask and CMP work, plus workfunction by using different metals instead of doping them, noted Freeman. But Intel has shown that it’s manufacturable even with the extra CMP of the gate stack, "and TSMC and UMC wouldn’t have gone that way if they didn’t think the same," James said. And the argument against gate-last’s more restrictive design rules becomes moot at 20nm which will demand them anyway, so "you might as well bite the bullet and switch to gate-last," he said.

It’s no big deal, compared to other things. The Common Platform Alliance says that it’s been evaluating both gate-first and gate-last since 2001 (gate-first was selected back in 2004). Speaking at the CPA forum, Gary Patton, IBM VP, said the replacement gate process isn’t his primary concern at 20nm — it’s other things that will come into play including self-aligned contacts, local interconnects, and BEOL pitches.

Patton noted that early 20nm production is slated for 1Q13, using third-generation ArF immersion litho with double patterning and source-mask optimization (SMO) technology. The SMO, along with special mask design software, is key to their 20nm process, explained Gartner research VP Bob Johnson, because it allows fine-tuning of both the mask and light source. "My impression is that IBM and its partners have much more experience" implementing these technologies, he said. Chipworks’ James points out, though, that forms of SMO are already being used (e.g. dipole sources), Intel has talked about it — "and ASML have now made onto their supplier list."

It’s not over yet. The debate over gate-first vs. gate-last likely will get revisited again soon, as another tough technology choice is coming right around the corner at 14nm, says Gartner’s Wang. That node will require fully depleted structure, which can be made either with FinFETs or extremely thin SOI (ETSOI). The IBM-led CPA has championed use of SOI so they’d have a leg up there, while Intel and TSMC are on bulk CMOS and would likely choose FinFET, he suggested. Once again it’s a case of pros vs. cons: gate-first pushes transistor engineering limits, but gate-last is more challenging in terms of fab work. So while gate-last appears to be the winner at 20nm, beyond this node it’ll be up in the air again.


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