January 24, 2011 — Semiconductor Research Corporation (SRC) and researchers from Stanford University have developed a combination of elements that yields a unique nanostructure material for packaging. This advance should allow longer life for semiconductor devices while costing less than current state-of-the-art materials. In addition to chip manufacturers, several other industries could also gain greater product efficiencies from related thermal energy management technology.

Semiconductor manufacturers currently rely on tiny pins or thick solder to bond sections of the semiconductor in order for the device to perform. However, current solder materials tend to degrade and fail due to heat and mechanical stress. To continue the scaling of integrated circuits (ICs), SRC and Stanford have researched materials that provide a high thermal connectivity (comparable to copper) with the flexible compliance of foam. The answer has been created through a nanostructured thermal tape that conducts heat like a metal while allowing the neighboring materials to expand and contract with temperature changes (metals are too stiff to allow this). This ability to reduce chip temperatures while remaining compliant is a key breakthrough for electronic packaging.  

"A big roadblock to increasing the performance of modern chips is hot spots, or millimeter-sized regions of high power generation. This advance in nanostructured materials and methods will allow us to better cool these spots and serves as a key enabler for densification of computational circuitry," said Professor Ken Goodson, lead researcher for SRC at Stanford University. "This can help packaging to withstand the demands of Moore’s Law."

In addressing the challenges of miniaturization, the first line of defense for hot spots is the interface material. Incorporating nearly two decades of advanced research and simulations for problems at the packaging level — much of it funded by SRC — the Stanford team ultimately arrived at their unique combination of binder materials surrounding carbon nanotubes (CNTs). The researchers expect it to facilitate the highest thermal conduction and the most desirable level of elasticity of any known packaging solutions.

"This new thermal nanotape revolutionizes the chip’s heat sink contact," said Jon Candelaria, director of Interconnect and Packaging Sciences at SRC. "Instead of being forced to rely upon the properties of just a single material, this combination gives the integrated circuits industry an opportunity to circumvent severe performance limitations and continue to improve packaging without adding cost."

While the research was funded by members of SRC to enhance computer chips, demand for applications of this kind of thermal interface also is rising in other industries. For instance, several automotive-related companies hope to recover electrical power from hot exhaust gases in cars and trucks using thermoelectric energy converters but reliable interfaces are a problem. Professor Goodson leads a major grant from the National Science Foundation (NSF) Department of Energy Partnership on Thermoelectric Devices for Vehicle Applications, with the goal of transferring the SRC-funded interface work to vehicles.

Patents for the technology are pending. The next step in the research is to license the new methods and materials to advanced thermal-interface companies for application tailoring and commercialization. End users are expected to benefit from the technology by 2014.

For more information and details about the new packaging materials and methods, visit http://pubs.acs.org/doi/abs/10.1021/nl100443x and http://microheat.stanford.edu/publications/A119.pdf.

SRC is a university-research consortium for semiconductors and related technologies that defines industry needs, invests in, and manages the research that gives its members a competitive advantage in the dynamic global marketplace. For more information, visit www.src.org.