By Debra Vogler, senior technical editor
February 3, 2011 — Barbara De Salvo, Head of the Advanced Memory Technology Laboratory at Leti, discussed two papers presented by the consortium at IEEE’s International Electron Devices Meeting (IEDM 2010 12/6-12/8/10, San Francisco, CA) in a podcast interview with Debra Vogler, senior technical editor.
In paper #29.1 ("N-doped GeTe as performance booster for embedded phase-change memories"), the researchers reported on the impact of N-doping in GeTe as a way to boost data retention in phase-change memories (PCMs). The group found that light N-doping stabilizes the amorphous phase without sacrificing the programming performance. De Salvo notes that, though typical PCMs have data retention lifetimes of 10 years at <100°C, the researchers were able to achieve a data retention lifetime of 10 years at 154°C for GeTeN2% (Fig. 1).
|Figure 1. a) Data retention for the best performing GeTeN2%. Each characteristic is the geometric average of ~40 devices. Devices are written/measured at high temperature with identical RESET pulse (IRESET ~ 30mA/tRESET=100ns). A stringent fail criterion equal to half of initial RESET resistance is assumed and indicated in the figure. b) Arrhenius extrapolation @ 10 years for GST, GeTe and GeTeN devices: GeTeN2% extrapolated fail temperature @ 10 years is 154°C. SOURCE: Leti, IEDM 2010 paper 29.1|
De Salvo says that this new material for PCMs (N-doped GeTe) appears to be very promising for embedded applications. In particular, the new material addresses high-temperature reliability issues that occur in PCMs. Not only is the data retention reliability for the N-doped new material much higher, it also has a faster switching rate. The improved data retention at high temperature is pertinent for both automotive and consumer electronics applications, said De Salvo.
In paper #22.5 ("Investigation of the role of H-related defects in Al2O3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modeling"), Leti researchers used atomistic simulation to investigate the origin of traps in Al2O3 on charge-trap memory. They were able to show that leakage currents through Al2O3 layers with different deposition anneals are strictly correlated to the H content. Using quantum simulations in a TANOS device simulator, the group attained very good agreement between the model and device experimental data (Fig. 2).
|Figure 2. Simulated retention curves for TANOS memories, assuming no traps in Al2O3, or a trap assisted conduction using trap#1 parameters (corresponding to 700°C Al2O3 PDA) or trap#2 parameters (900°C Al2O3 PDA). Curves are simulated for two applied VG. SOURCE: Leti, IEDM 2010 paper 22.5|