February 2, 2011 – BUSINESS WIRE — Rambus Inc. (NASDAQ:RMBS), technology licensing company, has advanced differential signaling for SoC-to-memory interfaces to 20 gigabits per second (Gbps) and developed innovations that can extend single-ended memory signaling to 12.8Gbps. Rambus has also developed technologies to allow a seamless transition for memory architectures from single-ended to differential signaling as data rates rise to meet the performance requirements of future-generation graphics and gaming systems.
Rambus will demonstrate its breakthroughs in memory signaling technology at DesignCon 2011.
The latest technology advancements of Rambus’ Terabyte Bandwidth Initiative enable power efficiency and compatibility to single-ended memory architectures, including GDDR5 and DDR3. With the addition of FlexMode interface technology, a multi-modal, SoC memory interface PHY, supporting both differential and single-ended signaling, can be implemented in a single SoC package design with no additional pins. Rambus has achieved a power efficiency of 6 milliwatts (mW) per Gbps when operating at 20Gbps in a 40nm-process silicon test vehicle. These innovations address critical system challenges to extending signaling rates by addressing power efficiency and compatibility needs.
We have paved multiple paths that extend single-ended signaling beyond today’s limits and developed the means for a seamless transition to differential signaling, said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus. "By advancing data rates in an extremely power-efficient way, and enabling compatibility to current industry-standard memories, we have removed the technical and business barriers for customers to achieve unprecedented capabilities in their products."
Graphics cards and game consoles are the marquee performance products for consumers. The demand for photorealistic game play, 3D images, and a richer end-user experience is constantly pushing system and memory requirements higher. Today’s high-end graphics processors support as much as 128 gigabytes per second (GB/s) of memory bandwidth, and future generations will push memory bandwidth to upwards of one terabyte per second (TB/s), according to the company.
Through the Terabyte Bandwidth Initiative, Rambus has developed Fully Differential Memory Architecture (FDMA), FlexLink C/A and 32X data rate, and FlexMode interface technology, which enables support of both differential and single-ended memory interfaces in a single SoC package design. FlexMode technology achieves this with no additional pins through programmable assignment of signaling I/Os to either data or command/address.
Launched in November 2007, the Terabyte Bandwidth Initiative reflects Rambus’ ongoing commitment to innovation in cutting-edge performance memory architectures. The initiative serves as the foundation for future memory architectures that offer increased performance, higher and scalable data bandwidth, area optimization, enhanced signal integrity, and multi-modal capability for gaming, graphics and multi-core computing applications. Additional information on the Terabyte Bandwidth Initiative is available at www.rambus.com/terabyte.
Rambus specializes in the invention and design of architectures focused on enriching the end-user experience of electronic systems. Additional information is available at www.rambus.com.