SOI Consortium unveils FDSOI results

By Debra Vogler, senior technical editor

February 14, 2011 The SOI Industry Consortium recently announced results of an assessment and characterization of fully depleted silicon-on-insulator (FD-SOI) technology (Fig. 1). The study, which was based on the ARM Cortex processor as a prototyping vehicle, concluded that FD-SOI is able to address the increasing low-power, high-performance requirements for mobile and consumer applications. The project was a joint effort among the following consortium members: ARM, Globalfoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti.

Listen to Horacio Mendez’s interview: Download (iPhone/iPod users) or Play Now

Horacio Mendez, executive director of the SOI Industry Consortium, discusses how planar FD-SOI technology enables substantial improvements in performance and power consumption, in a podcast interview with Debra Vogler, senior technical editor. In particular, Mendez describes how it improves on the key metrics for mobile markets: power, frequency, manufacturability, and cost efficiency.

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FD-SOI benefits tailored for the mobile market:

  • Simpler technology, straightforward transistor architecture
  • No floating body to worry about
  • Better for SRAM design (lower power, better stability)
  • Better process control, and manufacturability (cost efficient)
Figure 1. FD-SOI transistor. SOURCE: SOI Consortium

Mendez also explains some of the physics behind the inherent stability of FD-SOI devices. In conventional (bulk) devices, implants are used to help control leakage and hit threshold voltage requirements. Because the location of the implants is not precise enough, the device will have random fluctuations that impact these parameters. “Because of the architecture of FD-SOI, implants are not needed to control the device threshold,” said Mendez. “So that gives you a very stable and predictable way to manufacture these devices and in turn.” In turn, he points out that this provides a very good value proposition for the bit cell and further explains the details in the podcast. Early benchmarks on FD-SOI technology demonstrate the ability to reduce the SRAM operating voltage by 100-150mV, thereby reducing memory power consumption up to 40% while maintaining the stability of the SRAM. 

  LP Bulk, 
Generation N
LP Bulk, 
Generation N +1
Generation N +1
VDD Normalized 
frequency to 1
Typical % 
  Additional % 
0.7 1 +25%   +80%
0.8 1 +25%   +40%
0.9 1 +25%   +25%

Figure 2. Comparison of traditional low power manufacturing technology processes from one node to another with the use of FD-SOI. SOURCE: SOI Consortium

Traditionally, low power manufacturing technology processes from one generation node to another yield a performance gain ranging from 20-30%. According to Mendez, the new evaluation indicates that when the same transition also includes FD-SOI technology an additional 80% gain can be achieved beyond the traditional increase (Fig. 2).

Mendez further pointed out that FD-SOI processing is simpler as it eliminates a number of mask layers during transistor-forming processing. Several companies have already announced their readiness to go into high-volume production with substrates (e.g., Soitec, SEH, MEMC).

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