Semiconductor manufacturers are now relying on immersion lithography for the 32 nm node, sometimes with double- and triple-patterning approached. Work progresses on EUV as the heir apparent, but e-beam lithography could emerge as a viable alternative. Since the issues are complex, we invited experts from imec, SEMATECH, Molecular Imprints, Cymer, and D2S to give their perspective on next generation lithography challenges and solutions.

Lithography – a technology outlook

Looking at the lithography landscape, I see three persisting trends. One is that EUV lithography is slowly maturing towards production-ready tools − too slowly, though to take over the main role before 2014. Luckily, 193nm immersion lithography keeps pushing the boundaries. It will most probably allow us to maintain the scaling pace until EUV is ready. And last and less prominent, there are a few alternative techniques for 193nm and EUV lithography. These, however, are unable to catch up with EUV, and currently trend towards their own niche: maskless e-beam lithography for mask writing; and nanoimprint lithography for hard drives. These three developments have their own dynamics, but they are bound together and driven by the scaling roadmap.

Kurt Ronse, Director, Lithography, imec, Leuven, Belgium

The issues that are holding back EUV are well known. There is the light source, which is being improved steadily, but which still doesn’t have near enough power for cost-effective production. The suppliers are making progress, albeit slower than they had anticipated in the first roadmaps.

Then there is the issue of mask inspection and defects. Here we have to distinguish between the more traditional absorber defects and so-called multilayer defects. For the absorber defects, we strongly believe that with today’s advanced patterned mask inspection tools, most absorber defects can be detected. This way, the R&D community has the tools to drive down the still rather high defect counts and should push for that. For the multilayer defects, on the other hand, the inspection tools are still under early development. I expect the first dedicated EUV mask inspection tools to be ready in 2013-2014. And as yield-effective production with EUV depends on these inspection tools, it is to be expected that the first production with EUV will not occur before 2014.

Another issue is the resists, but there, I don’t see a real showstopper. The road will be long and bumpy, but there is continuous progress. This is helped by the growing number of EUV exposure tools that have become available to test candidate resists. So given the available time window, I am fairly positive that suitable resists will be available.

In the meantime, 193nm immersion lithography is − nanometer by nanometer − surpassing all limits that we thought insurmountable just a few years ago.

The name of the game now is computational lithography, a basket of powerful computational tools that allow printing ever finer details, linked to ever more powerful scanner knobs. One example is ASML’s Flexray, but there are others in the making. The common characteristic of these techniques is that they look for potential "hot" spots in designs. They do this by simulating, with a precision down to a fraction of a nanometer, how a design will be printed by an actual scanner. So these computations take into account the characteristics of the actual scanner that will print the layout. By then tweaking the parameters of that scanner and rerunning the simulations, the scanner can be optimized for the design. In combination with double-patterning, computational lithography will allow us to print 22nm half pitch layouts.

In this overview, we can’t leave out the two technologies that are hailed as alternatives for EUV: e-beam maskless lithography and nanoimprint. In 2010 though, these technologies weren’t able to narrow the gap with EUV. For e-beam maskless lithography, the only tools available in 2010 were still pre-alpha. These serve mainly to prove the feasibility of using e-beam for chip production. And even that feasibility is restricted to resolution, and doesn’t include alignment, stitching, or overlay specs. But where we do see e-beam evolving is towards mask writing. Resolution is less of an issue here, as we are talking about 4x masks. What is more of a problem though is the throughput that these tools are capable of, as well as the pattern placement accuracy and stability. As for nanoimprint, the big issue still is the defectivity of the templates. How can defects be detected, and how can these templates be made defect-free, or can they be repaired? And there is also an issue with the lifetime of the templates, which seem to degrade through use. So yes, these technologies are alive and evolving, but I don’t see them catching up with EUV anytime soon.

2011 will see the introduction of ASML’s new generation of EUV tools, the NXE:3100. With these tools at hand, we will steadily advance EUV. In the meantime, the established 193nm lithography technology will serve us further, equipped with ever smarter additional computational knobs and handles.

EUV lithography enters development phase

The lithography community has long awaited the delivery of a commercial EUV tool to semiconductor manufacturing customers. At the October 2010 International Symposium on EUV Lithography, ASML announced the shipment of the first pre-production EUV scanner. With five more tools scheduled to be shipped by mid-2011 and confirmed orders for eight next-generation production EUV scanners, EUV lithography is poised to enter a new phase.

Bryan J. Rice, Director of Lithography, SEMATECH, Albany, NY USA

The arrival of commercial tools at chip makers signals the beginning of EUV development activities for companies hoping to implement manufacturing processes based on EUV lithography. Since EUV has previously been investigated only in research environments, the development stage is likely to uncover many new challenges. For example, EUV lithography using only a few reticles exposed on hundreds of wafers per year on full-field alpha tools will burgeon to the use of hundreds of reticles to expose tens of thousands of wafers on pre-production scanners.

Some longstanding EUV lithography hurdles still remain. Current scanners incorporating 15W sources with a 40% duty cycle permit throughputs of only ten wafers per hour, which will likely incite development organizations to demand more rapid improvement in source power. In fact, competing source suppliers are already providing alternatives, with at least one pre-production source order placed with Xtreme.

EUV mask blank defects have also remained a key impediment to the manufacturing readiness of EUV. Generally, EUV blank defectivity is between ten and 100 times too high for memory and logic applications, respectively. The problem stems from insufficient demand to fund the development of cleaner processes at blank suppliers coupled with the mask industry’s lack of a business model to support the timely investment in an infrastructure. In both cases, the arrival of development tools at chip manufacturers has been a catalyst: blank suppliers have been giving more credence to future blank sales forecasts while metrology suppliers have been more willing to make risky investments in developing new metrology tools. As a result, blank suppliers are responding to their customers with credible plans to meet yield and volume targets and metrology suppliers are building the necessary metrology tools.

The next phase of EUV technology evolution will, without doubt, involve the discovery of new implementation challenges. This is a natural consequence of the new environment in which EUV will find itself. More than ever, those companies looking toward the successful deployment of EUV—suppliers and customers alike—must be prepared to garner the considerable support needed to overcome emerging challenges. If EUV follows the trend of previous lithography technologies, it will be entering its most concentrated period of learning and improvement in the next two to three years.

Semiconductor consortia and many semiconductor companies have strategies to support this next phase of EUV development. In particular, SEMATECH is spearheading the EUV Mask Infrastructure (EMI) partnership to develop needed mask metrology tools. SEMATECH resources are also being deployed to maintain the leading-edge Resist and Materials Development Center as well as a strong Mask Blank Defect Reduction program. In industry, memory and logic chip manufacturers alike are launching or ramping up their EUV programs with the aim of having revenue-generating products as soon as 2012 or 2013. Likewise, suppliers are intensifying their EUV efforts. ASML’s announcement that they will be tripling EUV scanner production capability is a prime example.

The next few years will challenge EUV implementation efforts with dilemmas and opportunities. The industry will be watching.

An affordable future for lithography

With all eyes focused on the increasingly difficult challenges facing optical lithography, it is not surprising that relatively scant attention has been paid to the continuing and significant progress being made with other alternate lithographic technologies. In particular, nanoimprint lithography, despite delivering the industry’s best pattern fidelity in the 20nm regime at an exceptionally competitive cost-of-ownership (T. Higashiki, Toshiba, ConFab 2010), still remains very much the Cinderella of the lithography "Ball." I believe, however, that this picture is likely to significantly change in the coming years, driven by the consumer demands and business imperatives of some critical volume applications and markets.

Nick Stacey, Molecular Imprints, Inc., Austin, TX USA

The data storage/memory industry, in particular, continues to be pushed relentlessly by the demands made on mobile and cloud computing for digital content storage and consumption, so that device manufacturers need to a least maintain the aggressive cost-per-bit reductions that have hitherto proven so technically enabling and financially lucrative. Nowhere is this clearer than with flash memory, where such progress over the last decade has revolutionized the handheld market, resulting in NAND revenue growth from less than $1B in 2000, to an estimate of more than $18B forecast in 2010; a 38% growth over 2009 (iSuppli, November 2010). The challenge facing NAND manufacturers is that with leading devices already being fabricated using 20nm-class lithography, 2D lithographic scaling is fast running out of steam, so that paradigm shifts in both device architectures and lithography will soon become imperative to maintain necessary performance and cost trajectories. One thing is clear; the continued escalation in optical lithography capital and process costs associated with critical dimension shrinks will increasingly fail to translate into the lower bit-costs required.

In marked contrast, nanoimprint lithography offers the capability of sub-10nm patterning at substantially lower costs of ownership, pointing the way towards an affordable path to fabricating the hyper-dense memory arrays required by tomorrow’s mobile consumer – the key word being affordable.

Surely and steadily, nanoimprint lithography has been proving its suitability for such advanced applications and is building the infrastructure necessary for its adoption. For example, while defectivity performance remains the most significant single challenge facing nanoimprint’s adoption in the semiconductor space, recent electrical yield studies in the 20nm regime have demonstrated marked and encouraging progress. Furthermore, the recent demonstration of 10nm mix-and-match overlay performance (T. Higashiki, Toshiba, ConFab 2010) clearly moves nanoimprint lithography a step closer to performance compatibility with mainstream device-layer design requirements.

Also of note is the development, by Molecular Imprints, Inc. in conjunction with a large semiconductor manufacturing partner, of a high-volume manufacturing system based on its Jet and Flash Imprint Lithography (J-FIL) technology, scheduled for installation and evaluation in 2011. Supporting this, a mask replication system has also recently shipped to Dai Nippon Printing Co., a leading merchant mask supplier, where a manufacturing process is now being developed for imprint replica mask supply to leading nanoimprint customers and partners.

Outside of semiconductors, in rotating disk storage, work continues within all the major hard disk drive (HDD) suppliers to develop bit-patterning for replacement of the traditional non-patterned storage media in use today. This is a major yet necessary transition for manufacturers to maintain their areal density (i.e., cost-per-bit) roadmaps and the long-held advantages over flash-based solid-state storage, particularly as these solid-state devices begin to erode some of HDD’s traditional consumer markets. Nanoimprint is the only lithographic technology being seriously considered for this transition, combining again low cost of ownership with an ultra-high resolution patterning capability that has already demonstrated printed densities around 1Tb/in2 on disk substrates (Z. Ye, DISKCON USA 2010, Santa Clara).

Beyond memory and storage applications, nanoimprint lithography continues to take its low cost/high resolution capabilities to new markets. The potential to enhance light capture and/or emission through the use of photonic structuring remains of keen interest to both the solar and solid-state lighting industries. Similarly, the capability to fabricate precisely controlled, high resolution and high fidelity structures at low cost has sparked considerable interest among the advanced display, energy storage and even the pharmaceutical industries.

All in all, as one surveys the many existing and emerging opportunities for nanoimprint, it seems very likely that several of these application "glass slippers" will end up fitting our technology "Cinderella," so that in the years to come, I believe you should expect this technology to be much more in the lithography limelight.

Acknowledgments

Jet and Flash and J-FIL are trademarks of Molecular Imprints.

2nd generation EUV sources on target for HVM in 2012/2013

The need for cost-effective lithography drives high productivity from the lithography exposure tool and high power from the light source, whether it is an excimer laser or an EUV laser-produced plasma source. Excimer laser power and performance have contributed to the outstanding gains in lithography productivity and extendibility over the last two decades. The successful development of EUV LPP source technology is the beginning of a similar journey from development to high-volume manufacturing. This will ensure a continued progression of the printing capability of lithography tools toward higher pixel density per unit time.

Bruno La Fontaine Senior Director, EUV Lithography Applications, Cymer, San Diego, Calif.

One of the key challenges of EUV lithography is throughput. Because the reflective optics used for this technology has a finite reflectivity of ~70%, the transmission of the light from the source to the wafer, which is typically achieved with more than 11 reflections, is very small. This puts stringent power requirements on the EUV lithography light source.

EUV sources capable of delivering sufficient power to support high-volume manufacturing are achieved using laser-produced plasmas (LPP). The LPP source uses a pulsed high-power RF-pumped CO2 laser system (>10kW power) operating at a wavelength of 10.6μm and repetition rates of typically 50kHz. The laser beam is focused to a waist diameter of ~100μm onto tin-droplet targets inside a vacuum vessel. A droplet generator produces droplet sizes of about 30μm in diameter at the same repetition rate as the laser. The small droplet size minimizes the cost of the tin fuel and improves the effectiveness of debris mitigation by reducing the quantity of residual tin within the source chamber.

Droplets are generated at a speed in excess of 60m/s with inter-droplet timing stability better than 0.2% of the period. Droplet position is controlled with a closed-loop steering system using a feedback signal from targeting cameras in the plasma chamber. When irradiated by the laser, each tin droplet is evaporated, ionized and heated to the optimal temperature at which the plasma produces EUV photons most efficiently.

These photons are collected by a multi-layer coated ellipsoidal collector mirror, covering approximately five sr solid angle, and refocused to a point known as the intermediate focus (IF), where they can be used by the lithography exposure tool. Debris mitigation consisting of a hydrogen gas curtain is incorporated to protect the multi-layer coating on the collector from tin deposition and etching due to plasma ions, both of which would result in reflectivity loss and ultimately reduce collection efficiency and power output.

During the past several months, Cymer shipped a number of EUV LPP sources to customers for use in commercial EUV exposure tools. These EUV sources have been integrated in ASML NXE:3100 scanners. The EUV exposure power produced by this source is currently on the order of 20W and is expected to be 40W in the first quarter of 2011, and exceed 100W by mid-2011.

With the implementation of these sources in the field, significant learning was achieved and led to improvement of source availability to more than 70%. One of the main factors driving higher source uptime has been the progress in droplet generator yield and lifetime. Another important element of source availability is collector lifetime. Cymer has made considerable progress in extending collector lifetime over the past several months, but collector protection improvement continues to be one of the main remaining challenges.

As the first generation of EUV sources are being implemented in pilot lines, second-generation sources have been designed and are being developed. These will be capable of providing clean EUV exposure power levels exceeding 250W, and are expected to support high-volume manufacturing starting in the 2012-2013 timeframe.

Investment in e-beam

Mask costs are limiting semiconductor design starts. That used to be a controversial statement, but these days, very few would argue otherwise. This is a serious problem for the entire industry: fewer design starts mean fewer engineering jobs, fewer design tool sales, fewer masks, fewer wafers, fewer distributed parts and fewer assembled systems. But for 22nm and below process technologies, writing a set of masks that produce a high-yielding wafer – at any cost – is a real issue.

Aki Fujimura, CEO, D2S, Inc. and Managing Sponsor of the eBeam Initiative, San Jose, CA USA

Today, the leading approaches to lithography for 22nm and below process technologies take four different angles, yet all use e-beam technology: continuation of 193nm immersion (193i) lithography with multi-pattern and complex masks; extreme ultraviolet (EUV) lithography; nano-imprint lithography (NIL) technologies; and electron-beam direct-write (EbDW) technologies. Among these, EbDW technologies, being maskless, have a unique set of advantages, including both lower cost and higher accuracy.

Maskless equals more design starts

The cost of a mask set is all non-recurring engineering (NRE), which means that advanced-node designs that use masks must have a high certainty of either very high volume or very high price to offset the NRE costs. Maskless approaches, such as EbDW, incur a small percentage of the NRE costs of mask-based approaches.

One important source of growth for the semiconductor industry is derivative designs, which amortize the human engineering costs of platform development over several variations of the same basic chip. However, mask costs still apply to derivative designs, as long as any of the mask-based lithography technologies is employed. EbDW, offering greatly lowered NRE, makes derivative designs far more affordable, which should lead to more derivative design starts.

Throughput: the challenge for maskless

With all its attractive advantages, EbDW has always had one major drawback: write times. The challenge in bringing EbDW to the mainstream is to get the write-times down to a practical level. The shift from Gaussian to variable-shaped beam (VSB) resulted in a 100x write-time improvement. Going from VSB to character projection (CP) coupled with design for e-beam (DFEB) techniques netted an additional 20x improvement. Many groups have been working on this problem for quite a while, and the results so far are impressive.

E-beam direct write lithography for 22nm and beyond

Today, there are two distinct approaches to EbDW lithography – multi-column cell (MCC) and multiple beam solutions – as well a hybrid of the two. MCC lithography machines use multiple e-beam guns, each with independent VSB and CP writing within the same column to shoot different parts of the wafer simultaneously. MCC with higher current sources provides an additional 60X improvement in writing time over the current state-of-the-art CP writer. Multiple-beam solutions split an electron beam from a single source into thousands of beams that write simultaneously (in essence, creating bit-mapped images on the wafer surface). The hybrid approach uses a single source, which is split into a smaller number of multiple beams, each of which is a VSB or CP shot. All of these solutions target write times between five to 10 wafers per hour. Clustering 10 machines is considered a viable approach to high-volume production when compared to the high cost of EUV lithography.

EbDW will become mainstream for maskless solutions only when multiple semiconductor manufacturers each invest in multiple machines. Today, the industry as a whole is still in a standoff in terms of investment in EbDW, with everyone waiting for someone to be the first mover.

E-beam is the future

Whichever of the EbDW solutions develop into mainstream solutions, it’s clear that e-beam has a bright future. Even if one or more of the mask-based approaches continue as a more practical approach to advanced-node wafer production, advanced e-beam machines will still be needed to create those masks.

Both governmental and private sector investors should be supporting the growth and development of e-beam technologies because lower mask cost supports the growth of the entire semiconductor industry. Investment in e-beam is an investment in the future of semiconductor, no matter which lithography method is used.

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