Qcept Technologies, Atlanta, GA USA
For many years the main driving force behind semiconductor innovation has been lithography with the migration to shorter wavelengths and adoption of new resists and methodologies. Each lithographic transition has brought new defect challenges, and billions of dollars have been invested by the semiconductor industry to address them.
Today, another process has become just as critical as lithography—wafer cleaning. Wafer cleaning and surface preparation are the most repeated steps in the fab—up to 100 times per wafer—which means there are many opportunities for a sub-optimal cleaning process to cause catastrophic yield loss.
The goal of wafer cleaning is pretty straight-forward: clean the wafer aggressively enough to remove unwanted material without damaging the underlying structures or substrate. When dealing with fairly robust materials such as oxide dielectrics and traditional planar features, this was relatively easy to accomplish and the process latitude afforded to the wafer cleaning process was wide. Because of this, wafer cleaning had been seen as an afterthought in the lithography, etch and CMP process modules for many years. That is no longer the case. With the adoption of exotic new materials and device structures to improve chip performance at the 22nm node and beyond, this process latitude has narrowed considerably.
Nowadays, if wafer cleaning is even slightly less aggressive than optimal, residues can remain that impact device yield and performance. If on the other hand the process is even slightly too aggressive, the circuitry underneath can be damaged. Cleaning has always included a balance of physical and chemical processes to dislodge residues and carry them away from the wafer’s surface. Using a more aggressive chemistry means that less physical force is needed, but more aggressive chemistries can attack the underlying material—leading to unwanted damage.
Take for example new low-k dielectric films, which are highly porous—making them extremely fragile and susceptible to absorbing surrounding materials. Wafer cleaning can potentially damage these films or change their dielectric constant, either of which impacts device performance. In addition, the transition from polysilicon to metal gates at the 22nm node creates new wafer cleaning challenges. These new gate structures are only a few nanometers thick. As a result, the removal of even a few molecules of material from the film’s surface during the wafer cleaning process can negatively impair device performance.
The industry has introduced physical methods, such as single-wafer (spray) cleans and acoustic (megasonic) vibration, to increase the physical action on the wafer surface, allowing less aggressive chemistries to be used. However, this can have the unwanted effect of physical damage to the underlying structure. Extremely thin high-k/metal gate films are more susceptible to charge buildup on the surface caused by sprays in single-wafer cleans tools. New multi-gate structures like FinFETs, which have very high aspect ratios, are susceptible to damage from acoustic-based wafer cleaning processes due to the physical forces generated by the acoustic waves, which can topple the structures.
The result is an ever-more-challenging balance between chemistry and physical methods to provide complete cleaning without causing underlying damage—causing more challenging yield management. In the "good old days" it was possible to determine a good or bad clean from particle inspection alone. This is no longer the case at the 22nm node. Surface anomalies that arise from sub-optimal cleans are invisible to traditional inline yield management methods, such as optical wafer inspection, since they do not scatter light.
With all of these challenges, it’s no surprise that wafer cleaning has moved front-and-center as the next major process frontier facing today’s leading chipmakers. At the most advanced fabs, yield and process engineering groups are working side-by-side to not only design the process, but ensure that their yield management strategy keeps pace by incorporating new methods for finding non-visual defects emerging at the 22nm node and beyond.
Ralph Spicer is VP of marketing at Qcept Technologies, 75 Fifth St. NW, Suite 740, Atlanta, GA 30308; ph.: 404-685-9434; email [email protected]