March 9, 2011 – BUSINESS WIRE — SEMATECH experts reported new breakthroughs in wafer bonding at the 7th Annual IMAPS Device Packaging Conference (DPC), March 7-10 in Scottsdale, AZ. Low-temp die tacking has yielded faster die-to-wafer integration.

Technologists from SEMATECH’s 3D Interconnect program have demonstrated a novel die-to-wafer interconnect process using a die-tacking and collective-bonding approach on a 300mm wafer platform for 3D-IC applications. Composite wafers containing a 50µm thin through-silicon-via (TSV) wafer attached to a supporting handle wafer were populated with die using a short, low-temperature tacking process. This process enables a faster method of die-to-wafer integration needed for the advancement of heterogeneous 3D-ICs.

Wafer-to-wafer (WtW) bonding is a key enabling process step for 3D interconnection of wafers through stacking. The International Technology Roadmap for Semiconductors (ITRS) roadmap for high density, intermediate level, TSVs specifies via diameters of 0.8 to 4.0µm in 2012 and beyond.

3D ICs will play an important role in the semiconductor industry, given their potential to alleviate scaling limitations, increase performance and functionality, and reduce cost. New and improved technologies and integration schemes will be necessary to realize 3D’s potential as a manufacturable and affordable path to sustaining semiconductor productivity growth.

Additionally, Sitaram Arkalgud presented a summary of SEMATECH’s programs in 3D IC technology development and emerging standards at the Global Business Council Spring Conference, held in conjunction with DPC. Arkalgud delivered an invited talk highlighting SEMATECH’s 3D Enablement program and a summary on how it will enable industry-wide ecosystem readiness for cost-effective TSV-based stacked IC solutions.

SEMATECH’s 3D program was established at CNSE’s Albany NanoTech Complex to deliver robust 300mm equipment and process technology solutions for high-volume TSV manufacturing. SEMATECH established the 3D Enablement program to drive cohesive industry standardization efforts and technical specifications for heterogeneous 3D integration. Administered by SEMATECH’s 3D Interconnect program, in partnership with SIA and SRC, the program is developing technologies and specifications necessary for establishing standards in critical areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling. SEMATECH is an international consortium of leading semiconductor manufacturers. Learn more at www.sematech.org

More news from IMAPS Device Packaging:

• Optomec aerosol jet printing featured as wire bond, TSV alternative at IMAPS Device Packaging
• Silicon interposers, embedded capacitors subject of ALLVIA presentation at IMAPS Device Packaging

Subscribe to Solid State Technology/Advanced Packaging.

Follow Advanced Packaging on Twitter.com by clicking www.twitter.com/advpackaging. Or join our Facebook group