SPIE keynote: imec stance on materials innovation

March 9, 2011 — Luc Van den hove, president/CEO of imec, summarizes key themes from his keynote presentation at the SPIE Advanced Lithography symposium (Feb. 28 – March 3 in San Jose, CA), in a podcast interview with SST senior technical editor Debra Vogler.

Listen to the interview:  Download (iPod/iPhone users) or Play Now

With the industry moving away from geometry-based scaling comes new challenges for materials (e.g. scaling gate oxides), and new innovations, such as stressors in the S/D and high-k/metal gates (HKMG). (Intel was first to use HKMG at the 45nm node, and others are now adopting it for 32nm and 28nm — and their struggles with it illustrate how difficult the integration is, he notes.) Beyond the ~4Xnm node we will likely need a whole new set of materials, including germanium and III-V materials in the transistor channel.

Van den hove also addresses silicon photonics as the most likely route to connecting stacked chips (e.g. memory and CPUs), and why the industry now has an opportunity to break out of its traditional core markets (consumer, computers, communications) and make real differences in important fields such as healthcare (e.g., patient monitoring and eventually implantable electronics).

More from SPIE Advanced Lithography:


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